Cheri-research/FAT-Allocator
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Akilan Selvacoumar
2025-01-20 13:34:14 +00:00
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% Created 2025-01-16 Thu 15:20
% Created 2025-01-17 Fri 15:29
% Intended LaTeX compiler: pdflatex
\documentclass[11pt]{article}
\usepackage[utf8]{inputenc}
@@ -27,7 +27,7 @@
\tableofcontents
\section{Evaluation}
\label{sec:orgdc1fb32}
\label{sec:org3be955b}
We conducted tests of the FAT Pointer-based range addresses against Jemalloc\cite{jemalloc},
the default memory allocator for CHERIBSD\cite{cheribsd}, to assess the performance improvements
@@ -68,7 +68,7 @@ gains were marginal or where it introduced additional complexity in memory manag
limitations provide a roadmap for future optimizations and refinements of the allocator design.
\subsection{Expirement setup}
\label{sec:org1821dc1}
\label{sec:orgeb993d4}
The CHERI Morello\cite{Morello} board was used to evaluate the proposed memory allocator.
Morello implements the ARM A76 with enhanced server-class memory, featuring a
@@ -99,7 +99,7 @@ us to compare the performance of the two allocators and assess the impact of
the proposed changes.
\begin{table}[htbp]
\caption{\label{tab:orgba41311}ARM performance counters}
\caption{\label{tab:org246a883}ARM performance counters}
\centering
\begin{tabular}{|l|l|}
\hline
@@ -141,12 +141,12 @@ Wall clock & The actual time taken from the start of a \\
\end{table}
\subsubsection{Benchmarks}
\label{sec:org76c5486}
\label{sec:orgf614dbb}
The benchmarks\cite{Benchmark} are classified into 2 classes:
\begin{enumerate}
\item Micro benchmark
\label{sec:org2f3b3d3}
\label{sec:org41c278c}
\begin{itemize}
\item GLIBC: The Glibc benchmark evaluates the performance of
malloc and free functions in single-threaded, multi-threaded,
@@ -163,7 +163,7 @@ doubles the working set size to analyze memory hierarchy behavior.
\end{itemize}
\item Macro runs
\label{sec:org1d39860}
\label{sec:org89020f2}
\begin{itemize}
\item Kmeans: Kmeans implements a parallelized K-means clustering algorithm that
assigns data points to clusters based on proximity to centroids,
@@ -182,15 +182,15 @@ timing help measure system performance and ensure correctness.
\end{enumerate}
\subsection{Results}
\label{sec:orgf4cf5db}
\label{sec:org921a6b3}
\begin{figure}[htbp]
\centering
\includegraphics[width=.9\linewidth]{./diagrams/bargraph.png}
\caption{\label{fig:org876b3c0}Percentage difference between the modified memory allocator against the default system memory allocator}
\caption{\label{fig:orga7f3598}Percentage difference between the modified memory allocator against the default system memory allocator}
\end{figure}
The graph[\ref{fig:org876b3c0}] highlights the performance comparison between the modified memory allocator and
The graph[\ref{fig:orga7f3598}] highlights the performance comparison between the modified memory allocator and
Jemalloc, the default memory allocator. The FAT pointer memory allocator, specifically optimized
for use with huge pages, demonstrates a clear advantage in scenarios where memory allocation
patterns benefit from its design. The results align with expectations, showcasing the impact
@@ -220,7 +220,7 @@ bottlenecked by factors such as computation or I/O rather than memory translatio
\begin{figure}[htbp]
\centering
\includegraphics[width=.9\linewidth]{./diagrams/kmeans.png}
\caption{\label{fig:org5dab5a3}Kmeans COZ benchmark executed against various cluster sizes}
\caption{\label{fig:org8683315}Kmeans COZ benchmark executed against various cluster sizes}
\end{figure}
The K-means algorithm was executed with varying cluster sizes to evaluate the performance difference
@@ -251,7 +251,7 @@ behavior and guide future improvements to address such outliers. Despite the dev
cluster size of 2000, the overall results reaffirm the allocator's capability to maintain
consistent performance benefits across most scenarios.
\subsection{Usability}
\label{sec:orgb046e55}
\label{sec:orgd6ba6f0}
The FAT pointer memory allocator demonstrates significant potential for enhancing
memory management in systems that benefit from huge page optimizations. Its design
effectively reduces TLB misses, achieving up to 90\% fewer data TLB walks, L2 TLB reads,