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Underfull \vbox (badness 10000) has occurred while \output is active [] @@ -1414,7 +1414,7 @@ Underfull \vbox (badness 10000) has occurred while \output is active [] [7.7 <./diagram/bargraph.png> <./diagram/kmeans.png>] -Underfull \vbox (badness 1895) has occurred while \output is active [] +Underfull \vbox (badness 10000) has occurred while \output is active [] @@ -1440,10 +1440,6 @@ Class acmart Warning: CCS concepts are mandatory for papers over two pages. - -Overfull \vbox (1.152pt too high) has occurred while \output is active [] - - (/usr/local/texlive/2025/texmf-dist/tex/generic/stringenc/se-pdfdoc.def File: se-pdfdoc.def 2019/11/29 v1.12 stringenc: PDFDocEncoding ) @@ -1461,11 +1457,11 @@ Package rerunfilecheck Info: File `paper.out' has not changed. Here is how much of TeX's memory you used: 23990 strings out of 473190 393203 string characters out of 5715801 - 963407 words of memory out of 5000000 + 964253 words of memory out of 5000000 46170 multiletter control sequences out of 15000+600000 768506 words of font info for 442 fonts, out of 8000000 for 9000 1302 hyphenation exceptions out of 8191 - 90i,16n,131p,1002b,820s stack positions out of 10000i,1000n,20000p,200000b,200000s + 90i,16n,131p,1002b,804s stack positions out of 10000i,1000n,20000p,200000b,200000s -Output written on paper.pdf (9 pages, 701276 bytes). +Output written on paper.pdf (9 pages, 701842 bytes). PDF statistics: 292 PDF objects out of 1000 (max. 8388607) 243 compressed objects within 3 object streams diff --git a/docs/EuroSys/Paper/paper.pdf b/docs/EuroSys/Paper/paper.pdf index ee70132..1f36b3b 100644 Binary files a/docs/EuroSys/Paper/paper.pdf and b/docs/EuroSys/Paper/paper.pdf differ diff --git a/docs/EuroSys/Paper/paper.tex b/docs/EuroSys/Paper/paper.tex index 2fed952..ed4756f 100644 --- a/docs/EuroSys/Paper/paper.tex +++ b/docs/EuroSys/Paper/paper.tex @@ -235,7 +235,7 @@ and the use of huge pages. Concurrently, advancements in hardware-level system security—exemplified by the Capability Hardware Enhanced RISC Instructions (CHERI) architecture—offer additional opportunities for improving TLB performance. CHERI introduces capability-based addressing, a novel approach that enhances system security by associating capabilities with memory pointers. By leveraging capability-based - addressing, memory allocators can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that + addressing, we introduce a memory allocator that can integrate block-based allocations within huge pages. Through our evaluation using both micro and macro benchmarks, we show that our allocator can reduce TLB misses by up to 90\%, leading to improvements in wall clock runtimes for memory-intensive applications. \end{abstract} @@ -342,13 +342,13 @@ workloads that rely heavily on large datasets. Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI) ~\cite{woodruff_cheri_2014} architecture, present additional opportunities for performance enhancement. CHERI's capability-based addressing approach not only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management -operations. By integrating CHERI’s compressed~\cite{woodruff_cheri_2019} encoded bounds with the use of huge pages, We have shown it is possible to track and manage +operations. By integrating CHERI’s compressed encoded bounds~\cite{woodruff_cheri_2019} with the use of huge pages, We have shown it is possible to track and manage large, physically contiguous memory blocks without requiring numerous TLB entries. This combination reduces TLB pressure by minimising the number of entries required to map extensive memory regions, thereby decreasing TLB misses and improving address translation performance. -Furthermore, it accelerates memory-intensive tasks by reducing the overhead associated with managing fragmented or non-contiguous +Furthermore, it accelerates memory-intensive tasks by reducing the overhead associated with managing non-contiguous memory allocations. The contributions for the following paper are as follows: \begin{itemize} - \item \textbf{Fat pointer Based Range Addresses}: Introduces fat-pointers that include memory bounds, allowing + \item \textbf{Fat Addresses Translations}: Introduces fat-pointers that include memory bounds, allowing efficient tracking and management of physically contiguous memory regions (section ~\ref{sec:FatPointerTranslations}). \item \textbf{CHERI’s Capability-based Optimization}: Demonstrates how CHERI's architecture can be @@ -454,15 +454,21 @@ and abstraction extensions for scalable software compartmentalization. \section{Fat Address Translations} \label{sec:FatPointerTranslations} -Fat-pointer Address Translations, combined with the capabilities of the CHERI (Capability Hardware Enhanced RISC Instructions) -architecture, introduce robust memory safety and security features by incorporating additional metadata -with memory pointers. Fat-pointer Address Translations enhanced architecture utilizes concepts such as FlexPointer~\cite{chen_flexpointer_2023}, -Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to manage memory effectively. +This section talks about how Fat-pointer Address Translations uses the CHERI architecture to +bring about block based allocations in physically contiguous memory. Fat-pointer Address Translations +leverages techniques like FlexPointer~\cite{chen_flexpointer_2023} and Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to +achieve lesser pressure in the TLB. A key component +in this implementation is the use of range addresses with CHERI CC~\cite{woodruff_cheri_2019}. -Range addresses play a pivotal role within the Fat Address Translations implementation, defining memory -regions bounded by a starting address (Upper) and an ending address (Lower). -These range addresses are encoded within FAT-pointers, allowing for precise -control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to reduce the number of TLB operations needed. +% Fat-pointer Address Translations, combined with the capabilities of the CHERI +% architecture, introduce robust memory safety and security features by incorporating additional metadata +% with memory pointers. Fat-pointer Address Translations enhanced architecture uses concepts such as FlexPointer~\cite{chen_flexpointer_2023}, +% Range Memory Mapping (RMM)~\cite{karakostas_redundant_2015} to manage memory effectively. + +% Range addresses play a pivotal role within the Fat Address Translations implementation, defining memory +% regions bounded by a starting address (Upper) and an ending address (Lower). +% These range addresses are encoded within FAT-pointers, allowing for precise +% control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to reduce the number of TLB operations needed. % The functionality of ranges encompasses several key aspects: % \begin{itemize} @@ -486,6 +492,14 @@ control using CHERI CC~\cite{woodruff_cheri_2019} bounds over memory regions to % \end{minipage} \end{figure*} +Figure \ref{fig:HighOverviewArchitecture} illustrates a comparison between standard memory allocation (malloc()) and a proposed Fat-pointer Address +Translation method. The standard approach involves a C program interacting with a custom allocator, utilizing 48-bit +free virtual addresses and a TLB walk (L1, L2, L3) to achieve non-contiguous allocation in physical memory. +This typically results in more TLB entries and increased TLB misses increasing the reasoning to have more TLB walks. +In contrast, the Fat-pointer Address Translations method employs a custom allocator leveraging +physically contiguous memory by using CHERI to encode +bounds within the pointers and as show in the figure \ref{fig:HighOverviewArchitecture} there is almost no reliance on walking the TLB. + Figure \ref{fig:HighOverviewArchitecture} illustrates the methodology employed to use the CHERI 128-bit FAT-pointer scheme for facilitating