diff --git a/docs/FutureTasks/Plan/Plan.html b/docs/FutureTasks/Plan/Plan.html new file mode 100644 index 0000000..c228945 --- /dev/null +++ b/docs/FutureTasks/Plan/Plan.html @@ -0,0 +1,437 @@ + + + + + + + +‎ + + + + + +
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Table of Contents

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+ +
+
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+

1. Plan

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+

+This document describes about the upcoming PhD plan for the upcoming year with the reflection of the previous year. +

+
+ +
+

1.2. Highoverview of the previous plan:

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+
+
+

1.2.1. Phase 1: FAT-Pointer (Jul–Sep 2024)

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+
+
    +
  1. July 1–15 (2024)
    +
    +
      +
    • Debug L1 TLB misses
      • +
    • Run COZ benchmarks
      • +
    • Port kernel module to SnMalloc
      • +
    +
    +
    2. +
  2. July 15–30 (2024)
    +
    +
      +
    • Benchmark with SPEC & XSBench
      • +
    • Compare with SnMalloc variants
      • +
    +
    +
    3. +
  3. August (2024)
    +
    +
      +
    • Draft EuroSys paper
      • +
    +
    +
    4. +
  4. September (2024)
    +
    +
      +
    • Write thesis chapter
      • +
    • Finalize EuroSys submission
      • +
    +
    +
    5. +
+
+
+

1.2.2. Phase 2: RISC-V Integration (Oct 2024–May 2025)

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+
+
    +
  1. October–December (2024)
    +
    +
      +
    • Modify Bluespec to bypass TLB
      • +
    • Set up evaluation environment
      • +
    +
    +
    2. +
  2. Janurary–Feburary
    +
    +
      +
    • Evaluate FAT-Pointer on RISC-V
      • +
    • Draft and refine ISMM paper
      • +
    +
    +
    3. +
  3. March–May
    +
    +
      +
    • Address backlog
      • +
    • Extend thesis chapter
      • +
    +
    +
    4. +
+
+
+

1.2.3. Phase 3: Uni-Kernel (May 2025–September 2026)

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+
+
    +
  1. May–December 2025
    +
    +
      +
    • Port allocator to CHERI Uni-Kernel
      • +
    • Design and evaluate unified allocator
      • +
    • Draft OSDI paper
      • +
    +
    +
    2. +
  2. Janurary–September 2026
    +
    +
      +
    • Finalize full PhD thesis
      • +
    +
    +
    3. +
+
+
+
+

1.3. Current plan

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+
+
+

1.3.1. June to July (2025)

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+
    +
  • Working on modifications to BlueSpec BSV files of the CHERI Toooba architecture.
    • +
  • Setting up baremetal C benchmark against the BlueSpec simulator.
    • +
  • Supervisory team modifications to the EuroSys paper.
    • +
  • Progression month.
    • +
  • Send the EuroSys paper to the Glasgow CHERI team for feedback.
    • +
+
+
+
+

1.3.2. July to August (2025)

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+
    +
  • Heavy debugging of the Toooba core for potencial expected errors (Bypass TLB phase of the memory pipeline).
    • +
  • Finalising the C benchmark suite for the Toooba architecture.
    • +
  • Documenting Toooba work to reused for the 2nd paper.
    • +
  • End of July (Work on EuroSys paper).
    • +
+
+
+
+

1.3.3. August to September (2025)

+
+
    +
  • Heavy debugging of the Toooba core for potencial expected errors (Similar to July).
    • +
  • Finish writing for Toooba work the Abtract, Introduction and methodology of the paper.
    • +
  • Expect preliminary results of the Toooba expirment.
    • +
+
+
+
+

1.3.4. September to October (2025)

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+
    +
  • Publish EuroSys paper (FAT Allocator).
    • +
  • Start benchmarking Toooba work.
    • +
  • Parallel write up of the Evaluation section.
    • +
+
+
+
+

1.3.5. October to November (2025)

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+
    +
  • Start work on the 3rd expirement (Heavier evaluation of expirement 1 and 2).
    • +
  • Modification to replace mmap in TcMalloc and Mesh allocator
    • +
+
+
+
+

1.3.6. November to December (2025)

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+
    +
  • Strip away Huge page aware implementation from JeMalloc, TcMalloc and Mesh.
    • +
  • Analyse the amount intructions reduced.
    • +
  • Start writing paper 3 based on EuroSys paper.
    • +
+
+
+
+

1.3.7. December to Janurary (2025 to 2026)

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+
    +
  • Evaluation of paper 3.
    • +
  • Start writing thesis for Expirement 1 and 2.
    • +
+
+
+
+

1.3.8. Janurary to September (2026)

+
+
    +
  • Backlog catch up.
    • +
  • Paper publishing for Expirement 3.
    • +
  • Thesis write up phase.
    • +
+
+
+
+
+
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+

Author: Akilan

+

Created: 2025-06-11 Wed 21:46

+

Validate

+
+ + diff --git a/docs/FutureTasks/Plan/Plan.org b/docs/FutureTasks/Plan/Plan.org new file mode 100644 index 0000000..5561a72 --- /dev/null +++ b/docs/FutureTasks/Plan/Plan.org @@ -0,0 +1,89 @@ +* Plan +This document describes about the upcoming PhD plan for the upcoming year with the reflection of the previous year. + +** Link to Previous PhD plan: +https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf + +** Highoverview of the previous plan: + +*** Phase 1: FAT-Pointer (Jul–Sep 2024) +**** July 1–15 (2024) +- Debug L1 TLB misses +- Run COZ benchmarks +- Port kernel module to SnMalloc + +**** July 15–30 (2024) +- Benchmark with SPEC & XSBench +- Compare with SnMalloc variants + +**** August (2024) +- Draft EuroSys paper + +**** September (2024) +- Write thesis chapter +- Finalize EuroSys submission + +*** Phase 2: RISC-V Integration (Oct 2024–May 2025) +**** October–December (2024) +- Modify Bluespec to bypass TLB +- Set up evaluation environment + +**** Janurary–Feburary +- Evaluate FAT-Pointer on RISC-V +- Draft and refine ISMM paper + +**** March–May +- Address backlog +- Extend thesis chapter + +*** Phase 3: Uni-Kernel (May 2025–September 2026) +**** May–December 2025 +- Port allocator to CHERI Uni-Kernel +- Design and evaluate unified allocator +- Draft OSDI paper + +**** Janurary–September 2026 +- Finalize full PhD thesis + +** Current plan + +*** June to July (2025) +- Working on modifications to BlueSpec BSV files of the CHERI Toooba architecture. +- Setting up baremetal C benchmark against the BlueSpec simulator. +- Supervisory team modifications to the EuroSys paper. +- Progression month. +- Send the EuroSys paper to the Glasgow CHERI team for feedback. + +*** July to August (2025) +- Heavy debugging of the Toooba core for potencial expected errors (Bypass TLB phase of the memory pipeline). +- Finalising the C benchmark suite for the Toooba architecture. +- Documenting Toooba work to reused for the 2nd paper. +- End of July (Work on EuroSys paper). + +*** August to September (2025) +- Heavy debugging of the Toooba core for potencial expected errors (Similar to July). +- Finish writing for Toooba work the Abtract, Introduction and methodology of the paper. +- Expect preliminary results of the Toooba expirment. + +*** September to October (2025) +- Publish EuroSys paper (FAT Allocator). +- Start benchmarking Toooba work. +- Parallel write up of the Evaluation section. + +*** October to November (2025) +- Start work on the 3rd expirement (Heavier evaluation of expirement 1 and 2). +- Modification to replace mmap in TcMalloc and Mesh allocator + +*** November to December (2025) +- Strip away Huge page aware implementation from JeMalloc, TcMalloc and Mesh. +- Analyse the amount intructions reduced. +- Start writing paper 3 based on EuroSys paper. + +*** December to Janurary (2025 to 2026) +- Evaluation of paper 3. +- Start writing thesis for Expirement 1 and 2. + +*** Janurary to September (2026) +- Backlog catch up. +- Paper publishing for Expirement 3. +- Thesis write up phase. diff --git a/docs/FutureTasks/Plan/Plan.pdf b/docs/FutureTasks/Plan/Plan.pdf new file mode 100644 index 0000000..75542bc Binary files /dev/null and b/docs/FutureTasks/Plan/Plan.pdf differ diff --git a/docs/FutureTasks/Plan/Plan.tex b/docs/FutureTasks/Plan/Plan.tex new file mode 100644 index 0000000..9773911 --- /dev/null +++ b/docs/FutureTasks/Plan/Plan.tex @@ -0,0 +1,164 @@ +% Created 2025-06-11 Wed 21:46 +% Intended LaTeX compiler: pdflatex +\documentclass[11pt]{article} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{graphicx} +\usepackage{longtable} +\usepackage{wrapfig} +\usepackage{rotating} +\usepackage[normalem]{ulem} +\usepackage{amsmath} +\usepackage{amssymb} +\usepackage{capt-of} +\usepackage{hyperref} +\author{Akilan} +\date{\today} +\title{} +\hypersetup{ + pdfauthor={Akilan}, + pdftitle={}, + pdfkeywords={}, + pdfsubject={}, + pdfcreator={Emacs 30.1 (Org mode 9.7.11)}, + pdflang={English}} +\begin{document} + +\tableofcontents + +\section{Plan} +\label{sec:org6c6881e} +This document describes about the upcoming PhD plan for the upcoming year with the reflection of the previous year. +\subsection{Link to Previous PhD plan:} +\label{sec:org90425e4} +\url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf} +\subsection{Highoverview of the previous plan:} +\label{sec:orgd52e8f6} + +\subsubsection{Phase 1: FAT-Pointer (Jul–Sep 2024)} +\label{sec:org3a0652d} +\begin{enumerate} +\item July 1–15 (2024) +\label{sec:org6262009} +\begin{itemize} +\item Debug L1 TLB misses +\item Run COZ benchmarks +\item Port kernel module to SnMalloc +\end{itemize} +\item July 15–30 (2024) +\label{sec:org61cb46a} +\begin{itemize} +\item Benchmark with SPEC \& XSBench +\item Compare with SnMalloc variants +\end{itemize} +\item August (2024) +\label{sec:org4922e91} +\begin{itemize} +\item Draft EuroSys paper +\end{itemize} +\item September (2024) +\label{sec:orgc6ec8a4} +\begin{itemize} +\item Write thesis chapter +\item Finalize EuroSys submission +\end{itemize} +\end{enumerate} +\subsubsection{Phase 2: RISC-V Integration (Oct 2024–May 2025)} +\label{sec:orgb93b481} +\begin{enumerate} +\item October–December (2024) +\label{sec:org3843dc0} +\begin{itemize} +\item Modify Bluespec to bypass TLB +\item Set up evaluation environment +\end{itemize} +\item Janurary–Feburary +\label{sec:org7742f73} +\begin{itemize} +\item Evaluate FAT-Pointer on RISC-V +\item Draft and refine ISMM paper +\end{itemize} +\item March–May +\label{sec:org4107ba1} +\begin{itemize} +\item Address backlog +\item Extend thesis chapter +\end{itemize} +\end{enumerate} +\subsubsection{Phase 3: Uni-Kernel (May 2025–September 2026)} +\label{sec:org071836f} +\begin{enumerate} +\item May–December 2025 +\label{sec:org59607b0} +\begin{itemize} +\item Port allocator to CHERI Uni-Kernel +\item Design and evaluate unified allocator +\item Draft OSDI paper +\end{itemize} +\item Janurary–September 2026 +\label{sec:org9ad5ff2} +\begin{itemize} +\item Finalize full PhD thesis +\end{itemize} +\end{enumerate} +\subsection{Current plan} +\label{sec:orgc77e82b} + +\subsubsection{June to July (2025)} +\label{sec:orgfbae360} +\begin{itemize} +\item Working on modifications to BlueSpec BSV files of the CHERI Toooba architecture. +\item Setting up baremetal C benchmark against the BlueSpec simulator. +\item Supervisory team modifications to the EuroSys paper. +\item Progression month. +\item Send the EuroSys paper to the Glasgow CHERI team for feedback. +\end{itemize} +\subsubsection{July to August (2025)} +\label{sec:org37dfe11} +\begin{itemize} +\item Heavy debugging of the Toooba core for potencial expected errors (Bypass TLB phase of the memory pipeline). +\item Finalising the C benchmark suite for the Toooba architecture. +\item Documenting Toooba work to reused for the 2nd paper. +\item End of July (Work on EuroSys paper). +\end{itemize} +\subsubsection{August to September (2025)} +\label{sec:org6ef9a73} +\begin{itemize} +\item Heavy debugging of the Toooba core for potencial expected errors (Similar to July). +\item Finish writing for Toooba work the Abtract, Introduction and methodology of the paper. +\item Expect preliminary results of the Toooba expirment. +\end{itemize} +\subsubsection{September to October (2025)} +\label{sec:org673b597} +\begin{itemize} +\item Publish EuroSys paper (FAT Allocator). +\item Start benchmarking Toooba work. +\item Parallel write up of the Evaluation section. +\end{itemize} +\subsubsection{October to November (2025)} +\label{sec:org221ec49} +\begin{itemize} +\item Start work on the 3rd expirement (Heavier evaluation of expirement 1 and 2). +\item Modification to replace mmap in TcMalloc and Mesh allocator +\end{itemize} +\subsubsection{November to December (2025)} +\label{sec:org9df337d} +\begin{itemize} +\item Strip away Huge page aware implementation from JeMalloc, TcMalloc and Mesh. +\item Analyse the amount intructions reduced. +\item Start writing paper 3 based on EuroSys paper. +\end{itemize} +\subsubsection{December to Janurary (2025 to 2026)} +\label{sec:org8ca2c4c} +\begin{itemize} +\item Evaluation of paper 3. +\item Start writing thesis for Expirement 1 and 2. +\end{itemize} +\subsubsection{Janurary to September (2026)} +\label{sec:org51ee55c} +\begin{itemize} +\item Backlog catch up. +\item Paper publishing for Expirement 3. +\item Thesis write up phase. +\end{itemize} +\end{document} diff --git a/docs/FutureTasks/Plan/plan-1.org b/docs/FutureTasks/Plan/plan-1.org new file mode 100644 index 0000000..4c362ce --- /dev/null +++ b/docs/FutureTasks/Plan/plan-1.org @@ -0,0 +1,90 @@ +* Plan +This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year. + +** Link to Previous PhD Plan +https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf + +** Summary of the Previous Plan + +*** Phase 1: FAT-Pointer Mechanism (July–September 2024) +**** 1st–15th July 2024 +- Investigated causes of L1 TLB misses associated with contiguous memory allocation. +- Executed performance benchmarking using COZ on selected C programs. +- Ported the kernel module to support SnMalloc, the default allocator in CheriBSD. + +**** 15th–30th July 2024 +- Conducted benchmarking using the SPEC and XSBench suites. +- Performed comparative analysis with both baseline and modified SnMalloc implementations. + +**** August 2024 +- Initiated drafting of a manuscript for submission to EuroSys, focusing on the FAT-Pointer memory allocator. + +**** September 2024 +- Compiled and structured thesis chapter related to the FAT-Pointer architecture. +- Finalised and submitted the EuroSys paper. + +*** Phase 2: RISC-V Integration (October 2024 – May 2025) +**** October–December 2024 +- Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline. +- Configured the experimental platform and evaluation toolchain. + +**** January–February 2025 +- Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba). +- Commenced drafting of a technical paper for ISMM based on RISC-V integration results. + +**** March–May 2025 +- Addressed outstanding tasks and technical backlog. +- Continued development of the corresponding thesis chapter. + +*** Phase 3: Uni-Kernel Deployment (May 2025 – September 2026) +**** May–December 2025 +- Ported the memory allocator to a CHERI-enabled Uni-Kernel environment. +- Designed and implemented a unified memory allocator to support both kernel and user-level allocations. +- Initiated drafting of a manuscript targeted at OSDI. + +**** January–September 2026 +- Finalised documentation and submission of the PhD thesis. +- Submitted third research paper based on extended evaluation. + +** Current Research Plan + +*** June–July 2025 +- Refactored BlueSpec SystemVerilog (BSV) modules within the CHERI Toooba architecture. +- Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform. +- Incorporated supervisory team feedback into revisions of the EuroSys paper. +- Undertook formal progression review requirements. +- Submitted EuroSys manuscript to the CHERI research team at the University of Glasgow for preliminary feedback. + +*** July–August 2025 +- Engaged in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path. +- Finalised and validated the C benchmark suite for Toooba evaluation. +- Began technical documentation of the Toooba workflow, to support a second publication. +- Concluded revisions to the EuroSys paper by the end of July. + +*** August–September 2025 +- Continued debugging efforts within the Toooba memory subsystem. +- Drafted the abstract, introduction, and methodology sections of the second research paper. +- Aimed to generate preliminary experimental results for inclusion in the evaluation. + +*** September–October 2025 +- Published the EuroSys paper detailing the FAT-Pointer allocator. +- Commenced benchmarking of the Toooba design. +- Simultaneously drafted the evaluation and analysis sections of the second manuscript. + +*** October–November 2025 +- Initiated third experimental phase, aimed at deeper evaluation of prior experiments. +- Modified memory allocators (TcMalloc and Mesh) to remove reliance on `mmap`. + +*** November–December 2025 +- Stripped away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh. +- Analysed instruction-level reductions and performance implications. +- Commenced drafting of the third research paper, building on contributions from the EuroSys paper. + +*** December 2025 – January 2026 +- Conducted evaluation and profiling for the third paper. +- Commenced thesis chapter write-up for Experiments 1 and 2. + +*** January–September 2026 +- Continued thesis development and refinement across all experimental chapters. +- Finalised and submitted third manuscript for peer review. +- Prepared complete PhD dissertation for submission. diff --git a/docs/FutureTasks/Plan/plan-1.pdf b/docs/FutureTasks/Plan/plan-1.pdf new file mode 100644 index 0000000..7f23f10 Binary files /dev/null and b/docs/FutureTasks/Plan/plan-1.pdf differ diff --git a/docs/FutureTasks/Plan/plan-1.tex b/docs/FutureTasks/Plan/plan-1.tex new file mode 100644 index 0000000..8f00dc7 --- /dev/null +++ b/docs/FutureTasks/Plan/plan-1.tex @@ -0,0 +1,165 @@ +% Created 2025-06-11 Wed 22:18 +% Intended LaTeX compiler: pdflatex +\documentclass[11pt]{article} +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage{graphicx} +\usepackage{longtable} +\usepackage{wrapfig} +\usepackage{rotating} +\usepackage[normalem]{ulem} +\usepackage{amsmath} +\usepackage{amssymb} +\usepackage{capt-of} +\usepackage{hyperref} +\author{Akilan} +\date{\today} +\title{} +\hypersetup{ + pdfauthor={Akilan}, + pdftitle={}, + pdfkeywords={}, + pdfsubject={}, + pdfcreator={Emacs 30.1 (Org mode 9.7.11)}, + pdflang={English}} +\begin{document} + +\tableofcontents + +\section{Plan} +\label{sec:org0566484} +This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year. +\subsection{Link to Previous PhD Plan} +\label{sec:org9f71b80} +\url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf} +\subsection{Summary of the Previous Plan} +\label{sec:orgaa32ef2} + +\subsubsection{Phase 1: FAT-Pointer Mechanism (July–September 2024)} +\label{sec:org947ff17} +\begin{enumerate} +\item 1st–15th July 2024 +\label{sec:org4686601} +\begin{itemize} +\item Investigated causes of L1 TLB misses associated with contiguous memory allocation. +\item Executed performance benchmarking using COZ on selected C programs. +\item Ported the kernel module to support SnMalloc, the default allocator in CheriBSD. +\end{itemize} +\item 15th–30th July 2024 +\label{sec:orgb1cc375} +\begin{itemize} +\item Conducted benchmarking using the SPEC and XSBench suites. +\item Performed comparative analysis with both baseline and modified SnMalloc implementations. +\end{itemize} +\item August 2024 +\label{sec:orgc7132f0} +\begin{itemize} +\item Initiated drafting of a manuscript for submission to EuroSys, focusing on the FAT-Pointer memory allocator. +\end{itemize} +\item September 2024 +\label{sec:org735895d} +\begin{itemize} +\item Compiled and structured thesis chapter related to the FAT-Pointer architecture. +\item Finalised and submitted the EuroSys paper. +\end{itemize} +\end{enumerate} +\subsubsection{Phase 2: RISC-V Integration (October 2024 – May 2025)} +\label{sec:orgd874419} +\begin{enumerate} +\item October–December 2024 +\label{sec:orgc01cd5d} +\begin{itemize} +\item Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline. +\item Configured the experimental platform and evaluation toolchain. +\end{itemize} +\item January–February 2025 +\label{sec:org2f43abb} +\begin{itemize} +\item Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba). +\item Commenced drafting of a technical paper for ISMM based on RISC-V integration results. +\end{itemize} +\item March–May 2025 +\label{sec:orgca33d11} +\begin{itemize} +\item Addressed outstanding tasks and technical backlog. +\item Continued development of the corresponding thesis chapter. +\end{itemize} +\end{enumerate} +\subsubsection{Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)} +\label{sec:org03fcd08} +\begin{enumerate} +\item May–December 2025 +\label{sec:org2cdb782} +\begin{itemize} +\item Ported the memory allocator to a CHERI-enabled Uni-Kernel environment. +\item Designed and implemented a unified memory allocator to support both kernel and user-level allocations. +\item Initiated drafting of a manuscript targeted at OSDI. +\end{itemize} +\item January–September 2026 +\label{sec:org004e3d6} +\begin{itemize} +\item Finalised documentation and submission of the PhD thesis. +\item Submitted third research paper based on extended evaluation. +\end{itemize} +\end{enumerate} +\subsection{Current Research Plan} +\label{sec:orgd8dd9c2} + +\subsubsection{June–July 2025} +\label{sec:org6d3b5a5} +\begin{itemize} +\item Refactored BlueSpec SystemVerilog (BSV) modules within the CHERI Toooba architecture. +\item Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform. +\item Incorporated supervisory team feedback into revisions of the EuroSys paper. +\item Undertook formal progression review requirements. +\item Submitted EuroSys manuscript to the CHERI research team at the University of Glasgow for preliminary feedback. +\end{itemize} +\subsubsection{July–August 2025} +\label{sec:orgf0ae0c2} +\begin{itemize} +\item Engaged in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path. +\item Finalised and validated the C benchmark suite for Toooba evaluation. +\item Began technical documentation of the Toooba workflow, to support a second publication. +\item Concluded revisions to the EuroSys paper by the end of July. +\end{itemize} +\subsubsection{August–September 2025} +\label{sec:org81af15d} +\begin{itemize} +\item Continued debugging efforts within the Toooba memory subsystem. +\item Drafted the abstract, introduction, and methodology sections of the second research paper. +\item Aimed to generate preliminary experimental results for inclusion in the evaluation. +\end{itemize} +\subsubsection{September–October 2025} +\label{sec:org4296fa4} +\begin{itemize} +\item Published the EuroSys paper detailing the FAT-Pointer allocator. +\item Commenced benchmarking of the Toooba design. +\item Simultaneously drafted the evaluation and analysis sections of the second manuscript. +\end{itemize} +\subsubsection{October–November 2025} +\label{sec:org6827c47} +\begin{itemize} +\item Initiated third experimental phase, aimed at deeper evaluation of prior experiments. +\item Modified memory allocators (TcMalloc and Mesh) to remove reliance on `mmap`. +\end{itemize} +\subsubsection{November–December 2025} +\label{sec:orgab49ede} +\begin{itemize} +\item Stripped away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh. +\item Analysed instruction-level reductions and performance implications. +\item Commenced drafting of the third research paper, building on contributions from the EuroSys paper. +\end{itemize} +\subsubsection{December 2025 – January 2026} +\label{sec:org28a1815} +\begin{itemize} +\item Conducted evaluation and profiling for the third paper. +\item Commenced thesis chapter write-up for Experiments 1 and 2. +\end{itemize} +\subsubsection{January–September 2026} +\label{sec:org3b950ac} +\begin{itemize} +\item Continued thesis development and refinement across all experimental chapters. +\item Finalised and submitted third manuscript for peer review. +\item Prepared complete PhD dissertation for submission. +\end{itemize} +\end{document}