fixed references and clearer graph images

docs/evaluation/evaluation.bbl

@@ -0,0 +1,63 @@
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+\providecommand{\url}[1]{#1}
+\csname url@samestyle\endcsname
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+#2}}
+\providecommand{\BIBdecl}{\relax}
+\BIBdecl
+
+\bibitem{jemalloc}
+\BIBentryALTinterwordspacing
+{JEMALLOC}. [Online]. Available: \url{https://jemalloc.net/jemalloc.3.html}
+\BIBentrySTDinterwordspacing
+
+\bibitem{cheribsd}
+\BIBentryALTinterwordspacing
+Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial. [Online]. Available:
+  \url{https://www.cheribsd.org/tutorial/23.11/benchmark/index.html}
+\BIBentrySTDinterwordspacing
+
+\bibitem{Morello}
+\BIBentryALTinterwordspacing
+Department of computer science and technology – {CHERI}: The arm morello
+  board. [Online]. Available:
+  \url{https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello.html}
+\BIBentrySTDinterwordspacing
+
+\bibitem{BenchmarkABI}
+R.~N.~M. Watson, J.~Clarke, P.~Sewell, J.~Woodruff, S.~W. Moore, G.~Barnes,
+  R.~Grisenthwaite, K.~Stacer, S.~Baranga, and A.~Richardson, ``{Early
+  performance results from the prototype Morello microarchitecture},''
+  University of Cambridge, Computer Laboratory, 15 JJ Thomson Avenue, Cambridge
+  CB3 0FD, United Kingdom, phone +44 1223 763500, Tech. Rep. UCAM-CL-TR-986,
+  September 2023.
+
+\bibitem{PerformanceCounter}
+\BIBentryALTinterwordspacing
+Arm architecture reference manual for a-profile architecture. [Online].
+  Available: \url{https://developer.arm.com/documentation/ddi0487/latest}
+\BIBentrySTDinterwordspacing
+
+\bibitem{Benchmark}
+\BIBentryALTinterwordspacing
+{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
+  main · akilan1999/{CHERI}-allocator. [Online]. Available:
+  \url{https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c}
+\BIBentrySTDinterwordspacing
+
+\end{thebibliography}

docs/evaluation/evaluation.bib

@@ -3,4 +3,47 @@
 	url = {https://www.cheribsd.org/tutorial/23.11/benchmark/index.html},
 	urldate = {2024-06-07},
 	file = {Benchmark ABI - CheriBSD 23.11 new features tutorial:/Users/akilan/Zotero/storage/9BDKUW28/index.html:text/html},
+}
+
+@TechReport{BenchmarkABI,
+  author =       {Watson, Robert N. M. and Clarke, Jessica and Sewell, Peter
+                  and Woodruff, Jonathan and Moore, Simon W. and Barnes,
+                  Graeme and Grisenthwaite, Richard and Stacer, Kathryn and
+                  Baranga, Silviu and Richardson, Alexander},
+  title =        {{Early performance results from the prototype Morello
+                  microarchitecture}},
+  institution =  {University of Cambridge, Computer Laboratory},
+  address =      {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom,
+                  phone +44 1223 763500},
+  month =        {September},
+  year =         {2023},
+  number =       {UCAM-CL-TR-986}
+}
+
+@online{jemalloc,
+	title = {{JEMALLOC}},
+	url = {https://jemalloc.net/jemalloc.3.html},
+	urldate = {2025-01-15},
+	file = {JEMALLOC:/Users/akilan/Zotero/storage/QDEIEJ9N/jemalloc.3.html:text/html},
+}
+
+@online{Benchmark,
+	title = {{CHERI}-Allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at main · Akilan1999/{CHERI}-Allocator},
+	url = {https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c},
+	urldate = {2025-01-15},
+	file = {CHERI-Allocator/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c at main · Akilan1999/CHERI-Allocator:/Users/akilan/Zotero/storage/2X8ZJLND/glibc-bench.html:text/html},
+}
+
+@online{Morello,
+	title = {Department of Computer Science and Technology – {CHERI}: The Arm Morello Board},
+	url = {https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello.html},
+	urldate = {2025-01-16},
+	file = {Department of Computer Science and Technology – CHERI\: The Arm Morello Board:/Users/akilan/Zotero/storage/GCMNX8LY/cheri-morello.html:text/html},
+}
+
+@online{PerformanceCounter,
+	title = {Arm Architecture Reference Manual for A-profile architecture},
+	url = {https://developer.arm.com/documentation/ddi0487/latest},
+	urldate = {2025-01-15},
+	file = {Arm Architecture Reference Manual for A-profile architecture:/Users/akilan/Zotero/storage/BVZSP7HA/latest.html:text/html},
 }

docs/evaluation/evaluation.org

@@ -1,7 +1,5 @@
 * Evaluation
 
-#+bibliography: evaluation.bib
-
 #+BEGIN_COMMENT
 We tested the FAT Pointer based range addresses
 against Jemalloc the default memory allocator
@@ -29,8 +27,8 @@ into the following:
   on the evaluated results and limitations identified.
 #+END_COMMENT
 
-We conducted tests of the FAT Pointer-based range addresses against Jemalloc, 
-the default memory allocator for CHERIBSD[cite:@cheribsd], to assess the performance improvements 
+We conducted tests of the FAT Pointer-based range addresses against Jemalloc\cite{jemalloc}, 
+the default memory allocator for CHERIBSD\cite{cheribsd}, to assess the performance improvements 
 enabled by a CHERI-based huge page-aware allocator. Specifically, we evaluated 
 the reduction in TLB misses and its impact on overall 
 performance metrics, such as wall clock runtime.
@@ -42,7 +40,7 @@ detailed aspects of the allocator's behavior. Macro benchmarks, on the other han
 encompass larger, real-world C programs, allowing us to assess the allocator's 
 performance in more practical, real-world scenarios.
 
-The experiment setup details the software stack used for evaluation. It includes 
+The experiment setup section details the software stack used for evaluation. It includes 
 the specific configurations, compiler options, and system environment tailored 
 to benchmark the proposed allocator. This ensures consistency and repeatability 
 in our results, providing a solid foundation for meaningful comparisons.
@@ -70,11 +68,11 @@ limitations provide a roadmap for future optimizations and refinements of the al
 ** Expirement setup
 
 #+BEGIN_COMMENT
-The CHERI morello board was used to evaluate tehe proposed memory allocator.
+The CHERI morello board\cite{Morello} was used to evaluate tehe proposed memory allocator.
 Morello implements the ARM A76 with enhanced server class memory. The speciafication
 includes a quad core ARM CPU with capabilties. The L1 and L2 cache was modified to
 proliferate the capability bit. When compiling the C program for benchmarking
-the Benchmark ABI was used as recommended by the CHERI community as a compliation
+the Benchmark ABI\cite{BenchmarkABI} was used as recommended by the CHERI community as a compliation
 mode with the Clang compilier.
 
 The benchmark ABI was designed because the Morello
@@ -93,7 +91,7 @@ is Jemalloc. The measurements are done using the ARM performance counters as men
 in the following section. 
 #+END_COMMENT
 
-The CHERI Morello board was used to evaluate the proposed memory allocator. 
+The CHERI Morello\cite{Morello} board was used to evaluate the proposed memory allocator. 
 Morello implements the ARM A76 with enhanced server-class memory, featuring a 
 quad-core ARM CPU with capability extensions. The L1 and L2 caches were modified 
 to proliferate the capability bit, ensuring compatibility with CHERI's capability-based 
@@ -101,7 +99,7 @@ memory model. When compiling the C programs for benchmarking, the Benchmark ABI
 used as recommended by the CHERI community. This compilation mode was enabled using 
 the Clang compiler.
 
-The Benchmark ABI was specifically designed because the Morello branch predictor 
+The Benchmark ABI\cite{BenchmarkABI} was specifically designed because the Morello branch predictor 
 was not expanded to predict bounds. Consequently, a capability-based jump introduces 
 stalls in later PCC-dependent instructions until bounds are established. This issue 
 is particularly significant during dynamically linked calls and returns between 
@@ -116,13 +114,13 @@ failing to overwrite the C program at runtime with the intended malloc functions
 The second allocator was the standard OS memory allocator, which, in the case of
 CHERIBSD, is Jemalloc.
 
-Performance measurements were carried out using ARM performance counters to 
+Performance measurements were carried out using ARM performance counters\cite{PerformanceCounter} to 
 ensure accurate evaluation. These counters provided detailed metrics, allowing 
 us to compare the performance of the two allocators and assess the impact of 
 the proposed changes.
 
-*** Performance counters used
-                                           
+#+CAPTION: ARM performance counters
+#+NAME: fig:ARMPerformaneCounter
 +--------------------------------------------------+--------------------------------------------+
 | Performance counter                              | Description                                |
 +--------------------------------------------------+--------------------------------------------+
@@ -160,7 +158,7 @@ the proposed changes.
 +--------------------------------------------------+--------------------------------------------+
 
 *** Benchmarks
-The benchmarks are classified into 2 classes:
+The benchmarks\cite{Benchmark} are classified into 2 classes:
 
 **** Micro benchmark
 - GLIBC: The Glibc benchmark evaluates the performance of
@@ -194,7 +192,9 @@ The benchmarks are classified into 2 classes:
 ** Results
 #+ATTR_HTML: :align right
 #+ATTR_ORG: :align center
-[[./diagrams/allbenchmarks.png]]
+#+CAPTION: Percentage difference between the modified memory allocator against the default system memory allocator
+#+NAME: fig:bargraph
+[[./diagrams/bargraph.png]]
 
 #+BEGIN_COMMENT
 The graph above refers to the precentage difference between the modified
@@ -218,7 +218,7 @@ clock run times.
 #+END_COMMENT
 
 
-The graph above highlights the performance comparison between the modified memory allocator and 
+The graph[[[fig:bargraph]]] highlights the performance comparison between the modified memory allocator and 
 Jemalloc, the default memory allocator. The FAT pointer memory allocator, specifically optimized 
 for use with huge pages, demonstrates a clear advantage in scenarios where memory allocation 
 patterns benefit from its design. The results align with expectations, showcasing the impact 
@@ -247,6 +247,8 @@ bottlenecked by factors such as computation or I/O rather than memory translatio
 
 #+ATTR_HTML: :align right
 #+ATTR_ORG: :align center
+#+CAPTION: Kmeans COZ benchmark executed against various cluster sizes
+#+NAME: fig:Kmeans
 [[./diagrams/kmeans.png]]
 
 #+BEGIN_COMMENT
@@ -305,4 +307,7 @@ insights into the allocator's interaction with system-level caching and memory t
 While the allocator excels in scenarios emphasizing high memory throughput, its impact on 
 macro benchmarks is less pronounced. This suggests that its benefits are most relevant for 
 applications with frequent and intensive memory operations rather than those constrained by 
-computation or I/O bottlenecks.
+computation or I/O bottlenecks.
+
+\bibliographystyle{IEEEtran}
+\bibliography{evaluation.bib}

docs/evaluation/evaluation.tex

@@ -1,4 +1,4 @@
-% Created 2025-01-14 Tue 14:03
+% Created 2025-01-16 Thu 15:20
 % Intended LaTeX compiler: pdflatex
 \documentclass[11pt]{article}
 \usepackage[utf8]{inputenc}
@@ -27,10 +27,10 @@
 \tableofcontents
 
 \section{Evaluation}
-\label{sec:orgbbe52ec}
+\label{sec:orgdc1fb32}
 
-We conducted tests of the FAT Pointer-based range addresses against Jemalloc, 
-the default memory allocator for CHERIBSD(, ), to assess the performance improvements 
+We conducted tests of the FAT Pointer-based range addresses against Jemalloc\cite{jemalloc}, 
+the default memory allocator for CHERIBSD\cite{cheribsd}, to assess the performance improvements 
 enabled by a CHERI-based huge page-aware allocator. Specifically, we evaluated 
 the reduction in TLB misses and its impact on overall 
 performance metrics, such as wall clock runtime.
@@ -42,7 +42,7 @@ detailed aspects of the allocator's behavior. Macro benchmarks, on the other han
 encompass larger, real-world C programs, allowing us to assess the allocator's 
 performance in more practical, real-world scenarios.
 
-The experiment setup details the software stack used for evaluation. It includes 
+The experiment setup section details the software stack used for evaluation. It includes 
 the specific configurations, compiler options, and system environment tailored 
 to benchmark the proposed allocator. This ensures consistency and repeatability 
 in our results, providing a solid foundation for meaningful comparisons.
@@ -68,9 +68,9 @@ gains were marginal or where it introduced additional complexity in memory manag
 limitations provide a roadmap for future optimizations and refinements of the allocator design.
 
 \subsection{Expirement setup}
-\label{sec:org0672379}
+\label{sec:org1821dc1}
 
-The CHERI Morello board was used to evaluate the proposed memory allocator. 
+The CHERI Morello\cite{Morello} board was used to evaluate the proposed memory allocator. 
 Morello implements the ARM A76 with enhanced server-class memory, featuring a 
 quad-core ARM CPU with capability extensions. The L1 and L2 caches were modified 
 to proliferate the capability bit, ensuring compatibility with CHERI's capability-based 
@@ -78,7 +78,7 @@ memory model. When compiling the C programs for benchmarking, the Benchmark ABI
 used as recommended by the CHERI community. This compilation mode was enabled using 
 the Clang compiler.
 
-The Benchmark ABI was specifically designed because the Morello branch predictor 
+The Benchmark ABI\cite{BenchmarkABI} was specifically designed because the Morello branch predictor 
 was not expanded to predict bounds. Consequently, a capability-based jump introduces 
 stalls in later PCC-dependent instructions until bounds are established. This issue 
 is particularly significant during dynamically linked calls and returns between 
@@ -93,15 +93,14 @@ failing to overwrite the C program at runtime with the intended malloc functions
 The second allocator was the standard OS memory allocator, which, in the case of
 CHERIBSD, is Jemalloc.
 
-Performance measurements were carried out using ARM performance counters to 
+Performance measurements were carried out using ARM performance counters\cite{PerformanceCounter} to 
 ensure accurate evaluation. These counters provided detailed metrics, allowing 
 us to compare the performance of the two allocators and assess the impact of 
 the proposed changes.
 
-\subsubsection{Performance counters used}
-\label{sec:org9f2d2f7}
-
-\begin{center}
+\begin{table}[htbp]
+\caption{\label{tab:orgba41311}ARM performance counters}
+\centering
 \begin{tabular}{|l|l|}
 \hline
 Performance counter & Description \\
@@ -139,15 +138,15 @@ Wall clock & The actual time taken from the start of a \\
  & during a memory read operation.) \\
 \hline
 \end{tabular}
-\end{center}
+\end{table}
 
 \subsubsection{Benchmarks}
-\label{sec:org91388b2}
-The benchmarks are classified into 2 classes:
+\label{sec:org76c5486}
+The benchmarks\cite{Benchmark} are classified into 2 classes:
 
 \begin{enumerate}
 \item Micro benchmark
-\label{sec:orgf10bbbd}
+\label{sec:org2f3b3d3}
 \begin{itemize}
 \item GLIBC: The Glibc benchmark evaluates the performance of
 malloc and free functions in single-threaded, multi-threaded,
@@ -164,7 +163,7 @@ doubles the working set size to analyze memory hierarchy behavior.
 \end{itemize}
 
 \item Macro runs
-\label{sec:orgc073fbd}
+\label{sec:org1d39860}
 \begin{itemize}
 \item Kmeans: Kmeans implements a parallelized K-means clustering algorithm that
 assigns data points to clusters based on proximity to centroids,
@@ -183,13 +182,15 @@ timing help measure system performance and ensure correctness.
 \end{enumerate}
 
 \subsection{Results}
-\label{sec:org306bf15}
-\begin{center}
-\includegraphics[width=.9\linewidth]{./diagrams/allbenchmarks.png}
-\end{center}
+\label{sec:orgf4cf5db}
+\begin{figure}[htbp]
+\centering
+\includegraphics[width=.9\linewidth]{./diagrams/bargraph.png}
+\caption{\label{fig:org876b3c0}Percentage difference between the modified memory allocator against the default system memory allocator}
+\end{figure}
 
 
-The graph above highlights the performance comparison between the modified memory allocator and 
+The graph[\ref{fig:org876b3c0}] highlights the performance comparison between the modified memory allocator and 
 Jemalloc, the default memory allocator. The FAT pointer memory allocator, specifically optimized 
 for use with huge pages, demonstrates a clear advantage in scenarios where memory allocation 
 patterns benefit from its design. The results align with expectations, showcasing the impact 
@@ -216,9 +217,11 @@ beyond memory allocation, diluting the impact of the allocator's optimizations.
 the benefits of huge pages may be less pronounced for these workloads, as they are often 
 bottlenecked by factors such as computation or I/O rather than memory translation overhead.
 
-\begin{center}
+\begin{figure}[htbp]
+\centering
 \includegraphics[width=.9\linewidth]{./diagrams/kmeans.png}
-\end{center}
+\caption{\label{fig:org5dab5a3}Kmeans COZ benchmark executed against various cluster sizes}
+\end{figure}
 
 The K-means algorithm was executed with varying cluster sizes to evaluate the performance difference 
 between the FAT pointer allocator and the baseline allocator as the workload scales. This analysis 
@@ -248,7 +251,7 @@ behavior and guide future improvements to address such outliers. Despite the dev
 cluster size of 2000, the overall results reaffirm the allocator's capability to maintain 
 consistent performance benefits across most scenarios.
 \subsection{Usability}
-\label{sec:orgb4de289}
+\label{sec:orgb046e55}
 The FAT pointer memory allocator demonstrates significant potential for enhancing 
 memory management in systems that benefit from huge page optimizations. Its design 
 effectively reduces TLB misses, achieving up to 90\% fewer data TLB walks, L2 TLB reads, 
@@ -265,4 +268,7 @@ While the allocator excels in scenarios emphasizing high memory throughput, its
 macro benchmarks is less pronounced. This suggests that its benefits are most relevant for 
 applications with frequent and intensive memory operations rather than those constrained by 
 computation or I/O bottlenecks.
+
+\bibliographystyle{IEEEtran}
+\bibliography{evaluation.bib}
 \end{document}