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test whole program

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Akilan Selvacoumar
2025-08-18 15:11:36 +01:00
parent 5ea7b433c4
commit 8269b62f13
1 changed files with 2 additions and 2 deletions
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benchmarks/benchmarks/StressTestMalloc/glibc-bench.sh
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# sh build.sh
LD_PRELOAD=./libjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-cheri.stat ./glibc-bench.out
LD_PRELOAD=./regularjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-regular.stat ./glibc-bench.out
LD_PRELOAD=/home/akilan/Alloc-Test/Reverse/CHERI-Allocator/bin/libjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-jemalloc-cheri.stat ./glibc-bench.out
LD_PRELOAD=/home/akilan/Alloc-Test/Reverse/CHERI-Allocator/bin/regularjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-regular.stat ./glibc-bench.out