diff --git a/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c b/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c
index 0c46cd5..19699d4 100644
--- a/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c
+++ b/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c
@@ -24,8 +24,8 @@
 #include <sys/resource.h>
 #include "malloc.h"
 
-// #define malloc      MALLOCCHERI
-// #define free        FREECHERI
+#define malloc      MALLOCCHERI
+#define free        FREECHERI
 
 // #include "bench-timing.h"
 // #include "json-lib.h"
@@ -197,7 +197,7 @@ static void usage (const char *name)
 int
 main (int argc, char **argv)
 {
-  //INITREGULARALLOC();
+  INITREGULARALLOC();
   long size = 16;
   if (argc == 2)
     size = strtol (argv[1], NULL, 0);
diff --git a/benchmarks/benchmarks/StressTestMalloc/glibc-bench.sh b/benchmarks/benchmarks/StressTestMalloc/glibc-bench.sh
index 79697df..1812788 100644
--- a/benchmarks/benchmarks/StressTestMalloc/glibc-bench.sh
+++ b/benchmarks/benchmarks/StressTestMalloc/glibc-bench.sh
@@ -1,3 +1,5 @@
 # sh build.sh
-LD_PRELOAD=/home/akilan/Alloc-Test/Reverse/CHERI-Allocator/bin/libjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-jemalloc-cheri.stat ./glibc-bench.out
-LD_PRELOAD=/home/akilan/Alloc-Test/Reverse/CHERI-Allocator/bin/regularjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-regular.stat ./glibc-bench.out
\ No newline at end of file
+# LD_PRELOAD=/home/akilan/Alloc-Test/Reverse/CHERI-Allocator/bin/libjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-jemalloc-cheri.stat ./glibc-bench.out
+# LD_PRELOAD=/home/akilan/Alloc-Test/Reverse/CHERI-Allocator/bin/regularjemalloc.so time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-regular.stat ./glibc-bench.out
+
+time pmcstat -d -w 1 -p l1d_tlb_rd -p l2d_tlb_rd -p l1d_tlb_refill -p cpu_cycles -p dtlb_walk -p stall_backend -p ll_cache_miss_rd -o glibc-huge.stat ./glibc-bench.out
\ No newline at end of file