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\author{Akilan}
\date{\today}
\title{}
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\begin{document}

\tableofcontents

\section{Plan}
\label{sec:org0566484}
This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year.
\subsection{Link to Previous PhD Plan}
\label{sec:org9f71b80}
\url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf}
\subsection{Summary of the Previous Plan}
\label{sec:orgaa32ef2}

\subsubsection{Phase 1: FAT-Pointer Mechanism (July–September 2024)}
\label{sec:org947ff17}
\begin{enumerate}
\item 1st–15th July 2024
\label{sec:org4686601}
\begin{itemize}
\item Investigated causes of L1 TLB misses associated with contiguous memory allocation.
\item Executed performance benchmarking using COZ on selected C programs.
\item Ported the kernel module to support SnMalloc, the default allocator in CheriBSD.
\end{itemize}
\item 15th–30th July 2024
\label{sec:orgb1cc375}
\begin{itemize}
\item Conducted benchmarking using the SPEC and XSBench suites.
\item Performed comparative analysis with both baseline and modified SnMalloc implementations.
\end{itemize}
\item August 2024
\label{sec:orgc7132f0}
\begin{itemize}
\item Initiated drafting of a manuscript for submission to EuroSys, focusing on the FAT-Pointer memory allocator.
\end{itemize}
\item September 2024
\label{sec:org735895d}
\begin{itemize}
\item Compiled and structured thesis chapter related to the FAT-Pointer architecture.
\item Finalised and submitted the EuroSys paper.
\end{itemize}
\end{enumerate}
\subsubsection{Phase 2: RISC-V Integration (October 2024 – May 2025)}
\label{sec:orgd874419}
\begin{enumerate}
\item October–December 2024
\label{sec:orgc01cd5d}
\begin{itemize}
\item Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline.
\item Configured the experimental platform and evaluation toolchain.
\end{itemize}
\item January–February 2025
\label{sec:org2f43abb}
\begin{itemize}
\item Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba).
\item Commenced drafting of a technical paper for ISMM based on RISC-V integration results.
\end{itemize}
\item March–May 2025
\label{sec:orgca33d11}
\begin{itemize}
\item Addressed outstanding tasks and technical backlog.
\item Continued development of the corresponding thesis chapter.
\end{itemize}
\end{enumerate}
\subsubsection{Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)}
\label{sec:org03fcd08}
\begin{enumerate}
\item May–December 2025
\label{sec:org2cdb782}
\begin{itemize}
\item Ported the memory allocator to a CHERI-enabled Uni-Kernel environment.
\item Designed and implemented a unified memory allocator to support both kernel and user-level allocations.
\item Initiated drafting of a manuscript targeted at OSDI.
\end{itemize}
\item January–September 2026
\label{sec:org004e3d6}
\begin{itemize}
\item Finalised documentation and submission of the PhD thesis.
\item Submitted third research paper based on extended evaluation.
\end{itemize}
\end{enumerate}
\subsection{Current Research Plan}
\label{sec:orgd8dd9c2}

\subsubsection{June–July 2025}
\label{sec:org6d3b5a5}
\begin{itemize}
\item Refactored BlueSpec SystemVerilog (BSV) modules within the CHERI Toooba architecture.
\item Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform.
\item Incorporated supervisory team feedback into revisions of the EuroSys paper.
\item Undertook formal progression review requirements.
\item Submitted EuroSys manuscript to the CHERI research team at the University of Glasgow for preliminary feedback.
\end{itemize}
\subsubsection{July–August 2025}
\label{sec:orgf0ae0c2}
\begin{itemize}
\item Engaged in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path.
\item Finalised and validated the C benchmark suite for Toooba evaluation.
\item Began technical documentation of the Toooba workflow, to support a second publication.
\item Concluded revisions to the EuroSys paper by the end of July.
\end{itemize}
\subsubsection{August–September 2025}
\label{sec:org81af15d}
\begin{itemize}
\item Continued debugging efforts within the Toooba memory subsystem.
\item Drafted the abstract, introduction, and methodology sections of the second research paper.
\item Aimed to generate preliminary experimental results for inclusion in the evaluation.
\end{itemize}
\subsubsection{September–October 2025}
\label{sec:org4296fa4}
\begin{itemize}
\item Published the EuroSys paper detailing the FAT-Pointer allocator.
\item Commenced benchmarking of the Toooba design.
\item Simultaneously drafted the evaluation and analysis sections of the second manuscript.
\end{itemize}
\subsubsection{October–November 2025}
\label{sec:org6827c47}
\begin{itemize}
\item Initiated third experimental phase, aimed at deeper evaluation of prior experiments.
\item Modified memory allocators (TcMalloc and Mesh) to remove reliance on `mmap`.
\end{itemize}
\subsubsection{November–December 2025}
\label{sec:orgab49ede}
\begin{itemize}
\item Stripped away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh.
\item Analysed instruction-level reductions and performance implications.
\item Commenced drafting of the third research paper, building on contributions from the EuroSys paper.
\end{itemize}
\subsubsection{December 2025 – January 2026}
\label{sec:org28a1815}
\begin{itemize}
\item Conducted evaluation and profiling for the third paper.
\item Commenced thesis chapter write-up for Experiments 1 and 2.
\end{itemize}
\subsubsection{January–September 2026}
\label{sec:org3b950ac}
\begin{itemize}
\item Continued thesis development and refinement across all experimental chapters.
\item Finalised and submitted third manuscript for peer review.
\item Prepared complete PhD dissertation for submission.
\end{itemize}
\end{document}
