\begin{thebibliography}{10}

\bibitem{mittal_survey_2017}
Sparsh Mittal.
\newblock A survey of techniques for architecting {TLBs}.
\newblock 29(10):e4061.
\newblock \_eprint: https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.4061.

\bibitem{panwar_hawkeye_2019}
Ashish Panwar, Sorav Bansal, and K.~Gopinath.
\newblock {HawkEye}: Efficient fine-grained {OS} support for huge pages.
\newblock In {\em Proceedings of the Twenty-Fourth International Conference on
  Architectural Support for Programming Languages and Operating Systems}, pages
  347--360. {ACM}.

\bibitem{woodruff_cheri_2014}
Jonathan Woodruff, Robert~N.M. Watson, David Chisnall, Simon~W. Moore, Jonathan
  Anderson, Brooks Davis, Ben Laurie, Peter~G. Neumann, Robert Norton, and
  Michael Roe.
\newblock The {CHERI} capability model: revisiting {RISC} in an age of risk.
\newblock 42(3):457--468.

\bibitem{woodruff_cheri_2019}
Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert~M.
  Norton, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel~W. Filardo,
  A.~Theodore Markettos, Michael Roe, Peter~G. Neumann, Robert N.~M. Watson,
  and Simon~W. Moore.
\newblock {CHERI} concentrate: Practical compressed capabilities.
\newblock 68(10):1455--1469.

\bibitem{THP}
Juan Navarro.
\newblock Practical, transparent operating system support for superpages.

\bibitem{Shadow_superpages}
Cheol~Ho Park and Daeyeon Park.
\newblock Aggressive superpage support with the shadow memory and the
  partial-subblock tlb.
\newblock {\em Microprocessors and Microsystems}, 25(7):329--342, 2001.

\bibitem{DirectSegment}
Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark~D. Hill, and Michael~M.
  Swift.
\newblock Efficient virtual memory for big memory servers.
\newblock {\em SIGARCH Comput. Archit. News}, 41(3):237–248, June 2013.

\bibitem{karakostas_redundant_2015}
Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark~D.
  Hill, Kathryn~S. {McKinley}, Mario Nemirovsky, Michael~M. Swift, and Osman
  Ünsal.
\newblock Redundant memory mappings for fast access to large memories.
\newblock In {\em Proceedings of the 42nd Annual International Symposium on
  Computer Architecture}, pages 66--78. {ACM}.

\bibitem{chen_flexpointer_2023}
Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
\newblock {FlexPointer}: Fast address translation based on range {TLB} and
  tagged pointers.
\newblock 20(2):1--24.

\bibitem{TLBBehavoir}
Gokul~B. Kandiraju and Anand Sivasubramaniam.
\newblock Characterizing the d-tlb behavior of spec cpu2000 benchmarks.
\newblock {\em SIGMETRICS Perform. Eval. Rev.}, 30(1):129–139, June 2002.

\bibitem{jemalloc}
{JEMALLOC}.

\bibitem{cheribsd}
Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial.

\bibitem{Morello}
Department of computer science and technology – {CHERI}: The arm morello
  board.

\bibitem{BenchmarkABI}
Robert N.~M. Watson, Jessica Clarke, Peter Sewell, Jonathan Woodruff, Simon~W.
  Moore, Graeme Barnes, Richard Grisenthwaite, Kathryn Stacer, Silviu Baranga,
  and Alexander Richardson.
\newblock {Early performance results from the prototype Morello
  microarchitecture}.
\newblock Technical Report UCAM-CL-TR-986, University of Cambridge, Computer
  Laboratory, 15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom, phone
  +44 1223 763500, September 2023.

\bibitem{PerformanceCounter}
Arm architecture reference manual for a-profile architecture.

\bibitem{Benchmark}
{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
  main · akilan1999/{CHERI}-allocator.

\end{thebibliography}