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\author{Akilan}
\date{\today}
\title{}
\hypersetup{
 pdfauthor={Akilan},
 pdftitle={},
 pdfkeywords={},
 pdfsubject={},
 pdfcreator={Emacs 29.4 (Org mode 9.6.15)}, 
 pdflang={English}}
\begin{document}

\tableofcontents


\section*{Future work}
\label{sec:org4e66dc8}
This documents is decision making to highlight
potential paths to take for this PhD.
We will initially talk about the current expirement
which is a FAT pointer based memory allocator
and will then expand into 2 potential paths:

\begin{itemize}
\item Cheri RISCV to prevent using the TLB.
\item Allocator evaluation based on stripping instruction
calls for larger allocators like Jemalloc.
\end{itemize}


\subsection*{1. Current expirement: FAT pointer based range addresses}
\label{sec:orgb9d89c6}
\begin{center}
\includegraphics[width=.9\linewidth]{./HighOverviewArchitecture.drawio.png}
\label{orgb8f5fe3}
\end{center}

The objective of this expirement was to ensure we can use the CHERI bounds as
tracking mechanism of allocations instead of using multiple TLB entries. Using
this approach we can use a single Huge page entry with bounds to ensure that
the bounds (Which is the top and base address) can be extracted from the
pointer using the Cheri compressed bounds mechanism. We implemented a simple
allocator which uses this technique with a basic malloc and free.

\subsubsection*{Objectives}
\label{sec:org0ebfce1}
\begin{itemize}
\item How does the utilization of bounds for tracking memory
allocations, in addition to security purposes, affect
the run times and Translation Lookaside Buffer (TLB)
miss rates in modern computing systems ?

\item How does the implementation of bounds for seeking through
physically contiguous memory influence the complexity and
efficiency of standard memory allocators, particularly
those with advanced features such as transparent huge pages,
and what are the implications for system performance in terms
of execution speed, memory access latency, and resource
utilization?
\end{itemize}

\subsubsection*{Hardware}
\label{sec:org5c66697}
\begin{itemize}
\item ARM morello (Huge page size 1GB used)
\end{itemize}

\subsubsection*{Evaluation}
\label{sec:orga66e547}
    We conducted tests of the FAT Pointer-based range addresses against Jemalloc,
    the default memory allocator for CHERIBSD, to assess the
    performance improvements enabled by a CHERI-based huge page-aware
    alocator. Specifically, we evaluated the reduction in TLB misses
    and its impact on overall performance metrics, such as wall clock runtime.
    To comprehensively analyze the proposed allocator,
we categorized benchmarks into two classes which are micro and
macro benchmarks. Micro benchmarks comprise smaller C programs
designed to target specific al- locator patterns, enabling us
to evaluate detailed aspects of the allocator’s behavior.
Macro benchmarks, on the other hand, encompass larger,
realworld C programs, allowing us to assess the allocator’s
performance in more practical, real-world scenarios.

\subsubsection*{limitation}
\label{sec:org1aa7249}
\begin{itemize}
\item Using Huge page still requires a TLB entry which could be mitigated
(Refer to the FPGA work).
\item ARMv8 only supports using to virtual addresses so it's required to
bypass the TLB for address translation.
\end{itemize}


\subsection*{2. Cheri RISCV to prevent using the TLB}
\label{sec:orgcde003a}

\begin{center}
\includegraphics[width=200px]{./MainOverview.png}
\label{orgfab8f7b}
\end{center}

In the current ARM Morello setup, address
translations rely on the TLB. The future approach
on RISC-V Tooba involves storing the offset directly within the pointer.
This is possible due to CHERI’s capability model, which supports
fine-grained memory protection and can encode bounds within pointers.
Utilizing Bounds in CHERI for Block-Based Allocation:
CHERI capabilities allow pointers to carry metadata about memory bounds,
providing hardware-enforced memory safety. By encoding the offset
and bounds within the pointer, the system can directly access memory
without needing intermediate translations via the TLB. This enables the
implementation of a block-based allocator that can efficiently manage memory
allocations and deallocations within defined bounds. Bypassing the TLB in RISC-V Tooba.

\subsubsection*{Hardware modifications}
\label{sec:org4c2f4f3}
The Bluespec design of the RISC-V processor will be modified to allow
certain memory operations to bypass the TLB. This means that when a pointer
with encoded offset and bounds is used, the system can directly compute the
physical address from the capability information. This modification reduces the
dependency on the TLB, decreasing latency.
and improving performance, especially for frequent memory operations.

\subsection*{3. Allocator evaluation based on stripping instruction calls for larger allocators}
\label{sec:org08c9e01}

\begin{center}
\includegraphics[width=.9\linewidth]{./memory_allocator.drawio.png}
\label{orge9efcc8}
\end{center}
\end{document}
