\begin{thebibliography}{22}
\providecommand{\natexlab}[1]{#1}
\providecommand{\url}[1]{\texttt{#1}}
\expandafter\ifx\csname urlstyle\endcsname\relax
  \providecommand{\doi}[1]{doi: #1}\else
  \providecommand{\doi}{doi: \begingroup \urlstyle{rm}\Url}\fi

\bibitem[Lustig et~al.(2013)Lustig, Bhattacharjee, and Martonosi]{TLBHierarchy}
Daniel Lustig, Abhishek Bhattacharjee, and Margaret Martonosi.
\newblock Tlb improvements for chip multiprocessors: Inter-core cooperative
  prefetchers and shared last-level tlbs.
\newblock \emph{ACM Trans. Archit. Code Optim.}, 10\penalty0 (1), April 2013.
\newblock ISSN 1544-3566.
\newblock \doi{10.1145/2445572.2445574}.
\newblock URL \url{https://doi.org/10.1145/2445572.2445574}.

\bibitem[Mittal()]{mittal_survey_2017}
Sparsh Mittal.
\newblock A survey of techniques for architecting {TLBs}.
\newblock 29\penalty0 (10):\penalty0 e4061.
\newblock ISSN 1532-0634.
\newblock \doi{10.1002/cpe.4061}.
\newblock URL \url{https://onlinelibrary.wiley.com/doi/abs/10.1002/cpe.4061}.
\newblock \_eprint: https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.4061.

\bibitem[Panwar et~al.()Panwar, Bansal, and Gopinath]{panwar_hawkeye_2019}
Ashish Panwar, Sorav Bansal, and K.~Gopinath.
\newblock {HawkEye}: Efficient fine-grained {OS} support for huge pages.
\newblock In \emph{Proceedings of the Twenty-Fourth International Conference on
  Architectural Support for Programming Languages and Operating Systems}, pages
  347--360. {ACM}.
\newblock ISBN 978-1-4503-6240-5.
\newblock \doi{10.1145/3297858.3304064}.
\newblock URL \url{https://dl.acm.org/doi/10.1145/3297858.3304064}.

\bibitem[Woodruff et~al.({\natexlab{a}})Woodruff, Watson, Chisnall, Moore,
  Anderson, Davis, Laurie, Neumann, Norton, and Roe]{woodruff_cheri_2014}
Jonathan Woodruff, Robert~N.M. Watson, David Chisnall, Simon~W. Moore, Jonathan
  Anderson, Brooks Davis, Ben Laurie, Peter~G. Neumann, Robert Norton, and
  Michael Roe.
\newblock The {CHERI} capability model: revisiting {RISC} in an age of risk.
\newblock 42\penalty0 (3):\penalty0 457--468, {\natexlab{a}}.
\newblock ISSN 0163-5964.
\newblock \doi{10.1145/2678373.2665740}.
\newblock URL \url{https://doi.org/10.1145/2678373.2665740}.

\bibitem[Woodruff et~al.({\natexlab{b}})Woodruff, Joannou, Xia, Fox, Norton,
  Chisnall, Davis, Gudka, Filardo, Markettos, Roe, Neumann, Watson, and
  Moore]{woodruff_cheri_2019}
Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony Fox, Robert~M.
  Norton, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel~W. Filardo,
  A.~Theodore Markettos, Michael Roe, Peter~G. Neumann, Robert N.~M. Watson,
  and Simon~W. Moore.
\newblock {CHERI} concentrate: Practical compressed capabilities.
\newblock 68\penalty0 (10):\penalty0 1455--1469, {\natexlab{b}}.
\newblock ISSN 0018-9340, 1557-9956, 2326-3814.
\newblock \doi{10.1109/TC.2019.2914037}.
\newblock URL \url{https://ieeexplore.ieee.org/document/8703061/}.

\bibitem[Pham et~al.(2014)Pham, Bhattacharjee, Eckert, and Loh]{TLBReach}
Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, and Gabriel~H. Loh.
\newblock Increasing tlb reach by exploiting clustering in page translations.
\newblock In \emph{2014 IEEE 20th International Symposium on High Performance
  Computer Architecture (HPCA)}, pages 558--567, 2014.
\newblock \doi{10.1109/HPCA.2014.6835964}.

\bibitem[Navarro et~al.(2003)Navarro, Iyer, Druschel, and Cox]{THP}
Juan Navarro, Sitararn Iyer, Peter Druschel, and Alan Cox.
\newblock Practical, transparent operating system support for superpages.
\newblock \emph{SIGOPS Oper. Syst. Rev.}, 36\penalty0 (SI):\penalty0 89–104,
  December 2003.
\newblock ISSN 0163-5980.
\newblock \doi{10.1145/844128.844138}.
\newblock URL \url{https://doi.org/10.1145/844128.844138}.

\bibitem[Cornea et~al.(2003)Cornea, Harrison, and Tang]{IntelItanium}
Marius Cornea, John Harrison, and Ping Tak~Peter Tang.
\newblock Intel® itanium® floating-point architecture.
\newblock In \emph{Proceedings of the 2003 Workshop on Computer Architecture
  Education: Held in Conjunction with the 30th International Symposium on
  Computer Architecture}, WCAE '03, page 3–es, New York, NY, USA, 2003.
  Association for Computing Machinery.
\newblock ISBN 9781450347327.
\newblock \doi{10.1145/1275521.1275526}.
\newblock URL \url{https://doi.org/10.1145/1275521.1275526}.

\bibitem[Park and Park(2001)]{Shadow_superpages}
Cheol~Ho Park and Daeyeon Park.
\newblock Aggressive superpage support with the shadow memory and the
  partial-subblock tlb.
\newblock \emph{Microprocessors and Microsystems}, 25\penalty0 (7):\penalty0
  329--342, 2001.
\newblock ISSN 0141-9331.
\newblock \doi{https://doi.org/10.1016/S0141-9331(01)00125-9}.
\newblock URL
  \url{https://www.sciencedirect.com/science/article/pii/S0141933101001259}.

\bibitem[Basu et~al.(2013)Basu, Gandhi, Chang, Hill, and Swift]{DirectSegment}
Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark~D. Hill, and Michael~M.
  Swift.
\newblock Efficient virtual memory for big memory servers.
\newblock \emph{SIGARCH Comput. Archit. News}, 41\penalty0 (3):\penalty0
  237–248, June 2013.
\newblock ISSN 0163-5964.
\newblock \doi{10.1145/2508148.2485943}.
\newblock URL \url{https://doi.org/10.1145/2508148.2485943}.

\bibitem[Karakostas et~al.()Karakostas, Gandhi, Ayar, Cristal, Hill,
  {McKinley}, Nemirovsky, Swift, and Ünsal]{karakostas_redundant_2015}
Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark~D.
  Hill, Kathryn~S. {McKinley}, Mario Nemirovsky, Michael~M. Swift, and Osman
  Ünsal.
\newblock Redundant memory mappings for fast access to large memories.
\newblock In \emph{Proceedings of the 42nd Annual International Symposium on
  Computer Architecture}, pages 66--78. {ACM}.
\newblock ISBN 978-1-4503-3402-0.
\newblock \doi{10.1145/2749469.2749471}.
\newblock URL \url{https://dl.acm.org/doi/10.1145/2749469.2749471}.

\bibitem[Chen et~al.(2023)Chen, Tong, Yang, Yi, and
  Cheng]{chen_flexpointer_2023}
Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, and Xu~Cheng.
\newblock Flexpointer: Fast address translation based on range tlb and tagged
  pointers.
\newblock \emph{ACM Trans. Archit. Code Optim.}, 20\penalty0 (2), March 2023.
\newblock ISSN 1544-3566.
\newblock \doi{10.1145/3579854}.
\newblock URL \url{https://doi.org/10.1145/3579854}.

\bibitem[Davis et~al.(2019)Davis, Watson, Richardson, Neumann, Moore, Baldwin,
  Chisnall, Clarke, Filardo, Gudka, Joannou, Laurie, Markettos, Maste,
  Mazzinghi, Napierala, Norton, Roe, Sewell, Son, and Woodruff]{CheriABI}
Brooks Davis, Robert N.~M. Watson, Alexander Richardson, Peter~G. Neumann,
  Simon~W. Moore, John Baldwin, David Chisnall, Jessica Clarke,
  Nathaniel~Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie,
  A.~Theodore Markettos, J.~Edward Maste, Alfredo Mazzinghi, Edward~Tomasz
  Napierala, Robert~M. Norton, Michael Roe, Peter Sewell, Stacey Son, and
  Jonathan Woodruff.
\newblock Cheriabi: Enforcing valid pointer provenance and minimizing pointer
  privilege in the posix c run-time environment.
\newblock In \emph{Proceedings of the Twenty-Fourth International Conference on
  Architectural Support for Programming Languages and Operating Systems},
  ASPLOS '19, page 379–393, New York, NY, USA, 2019. Association for
  Computing Machinery.
\newblock ISBN 9781450362405.
\newblock \doi{10.1145/3297858.3304042}.
\newblock URL \url{https://doi.org/10.1145/3297858.3304042}.

\bibitem[Evans(2006)]{jemalloc}
Jason Evans.
\newblock A scalable concurrent malloc (3) implementation for freebsd.
\newblock In \emph{Proc. of the bsdcan conference, ottawa, canada}, 2006.

\bibitem[Evans()]{evans_scalable_nodate}
Jason Evans.
\newblock A {Scalable} {Concurrent} malloc(3) {Implementation} for {FreeBSD}.

\bibitem[che()]{cheribsd}
Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial.
\newblock URL
  \url{https://www.cheribsd.org/tutorial/23.11/benchmark/index.html}.

\bibitem[Ben()]{Benchmark}
{CHERI}-allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at
  main · akilan1999/{CHERI}-allocator.
\newblock URL
  \url{https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c}.

\bibitem[Mor()]{Morello}
Department of computer science and technology – {CHERI}: The arm morello
  board.
\newblock URL
  \url{https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello.html}.

\bibitem[Watson et~al.(2023)Watson, Clarke, Sewell, Woodruff, Moore, Barnes,
  Grisenthwaite, Stacer, Baranga, and Richardson]{BenchmarkABI}
Robert N.~M. Watson, Jessica Clarke, Peter Sewell, Jonathan Woodruff, Simon~W.
  Moore, Graeme Barnes, Richard Grisenthwaite, Kathryn Stacer, Silviu Baranga,
  and Alexander Richardson.
\newblock {Early performance results from the prototype Morello
  microarchitecture}.
\newblock Technical Report UCAM-CL-TR-986, University of Cambridge, Computer
  Laboratory, 15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom, phone
  +44 1223 763500, September 2023.

\bibitem[Per()]{PerformanceCounter}
Arm architecture reference manual for a-profile architecture.
\newblock URL \url{https://developer.arm.com/documentation/ddi0487/latest}.

\bibitem[Singh(1993)]{singh1993}
Jaswinder~Pal Singh.
\newblock \emph{Parallel Hierarchical N-body Methods and Their Implications for
  Multiprocessors}.
\newblock PhD thesis, Stanford University, February 1993.

\bibitem[Holt and Singh(1995)]{holt1995}
C.~Holt and Jaswinder~Pal Singh.
\newblock Hierarchical n-body methods on shared address space multiprocessors.
\newblock In \emph{SIAM Conference on Parallel Processing for Scientific
  Computing}, February 1995.
\newblock To appear.

\end{thebibliography}