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\author{Akilan}
\date{\today}
\title{}
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\begin{document}

\tableofcontents

\section{Plan}
\label{sec:org0b4a538}
This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year.
\subsection{Current experiments:}
\label{sec:org2ec96bb}
\begin{itemize}
\item (Experiment 1)FAT allocator with huge pages (EuroSys26 paper draft)
\item (Experiment 2)FAT allocator to bypass TLB. (Proposal of ongoing expirement)
\item (Experiment 3)Allocator evaluation based on stripping instruction calls from larger allocators. (Appendix)
\end{itemize}
\subsection{Experiment cancelled:}
\label{sec:orgbfb4e3d}
\begin{enumerate}
\item Uni-Kernel Development (Reason): Work scaled down to fit within the allocated within PhD timeframe and instead introduced an extension of the FAT allocator as the third experiment.
\end{enumerate}
\subsection{Link to the Previous PhD Plan}
\label{sec:org5e13e60}
\begin{itemize}
\item \url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf}
\end{itemize}
\subsection{Summary of the Previous Plan}
\label{sec:orgbef61d6}
\subsubsection{Phase 1: FAT-Pointer Mechanism (July–September 2024)}
\label{sec:orgc225731}
\begin{enumerate}
\item 1st to 15th July 2024
\label{sec:orga23a507}
\begin{itemize}
\item Investigated causes of L1 TLB misses associated with contiguous memory allocation.
\item Executed performance benchmarking using COZ\cite{coz} on selected C programs.
\item Ported the kernel module to support SnMalloc, the default allocator in CheriBSD.
\end{itemize}
\item 15th to 30th July 2024
\label{sec:orgdcdbfff}
\begin{itemize}
\item Conducted benchmarking using the SPEC and XSBench suites.
\item Performed comparative analysis with both baseline and modified SnMalloc implementations.
\end{itemize}
\item August 2024
\label{sec:org291b509}
\begin{itemize}
\item Initiated drafting of a paper for submission to EuroSys, focusing on the FAT-Pointer memory allocator (Current: On review stage).
\end{itemize}
\item September 2024
\label{sec:org8e3adb1}
\begin{itemize}
\item Compiled and structured thesis chapter related to the FAT-Pointer architecture.
\item Finalised and submitted the EuroSys paper.
\end{itemize}
\end{enumerate}
\subsubsection{Phase 2: RISC-V Integration (October 2024 – May 2025)}
\label{sec:orge4d0c50}
\begin{enumerate}
\item October to December 2024
\label{sec:orge79764e}
\begin{itemize}
\item Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline (Current: On progress).
\item Configured the experimental platform and evaluation toolchain (Current: On progress).
\end{itemize}
\item January to February 2025
\label{sec:orge05fc21}
\begin{itemize}
\item Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba) (Current: Todo).
\item Commenced drafting of a technical paper for ISMM based on RISC-V integration results (Current: Todo).
\end{itemize}
\item March to May 2025
\label{sec:org90e5eee}
\begin{itemize}
\item Addressed outstanding tasks and technical backlog.
\item Continued development of the corresponding thesis chapter.
\end{itemize}
\end{enumerate}
\subsubsection{Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)}
\label{sec:orgb30d702}
\begin{enumerate}
\item May to December 2025
\label{sec:orgd428eea}
\begin{itemize}
\item Ported the memory allocator to a CHERI-enabled Uni-Kernel environment (Current: Cancelled)
\item Designed and implemented a unified memory allocator to support both kernel and user-level allocations (Current: Cancelled)
\item Initiated drafting of a manuscript targeted at OSDI (Current: Cancelled)
\end{itemize}
\item January to September 2026
\label{sec:orga103287}
\begin{itemize}
\item Finalised documentation and submission of the PhD thesis (Current: New plan to still keep these dates unchanged)
\item Submitted third research paper based on extended evaluation (Current: Replaced with "Allocator evaluation based on stripping instruction calls from larger allocators")
\end{itemize}
\end{enumerate}
\subsection{Current Research Plan}
\label{sec:org055ec33}
This section outlines a comprehensive timeline of research activities and academic milestones to be undertaken between June 
2025 and September 2026 as part of the PhD to be focused on the CHERI Toooba architecture\cite{Toooba}. It includes the refactoring of BlueSpec\cite{bluespec} SystemVerilog\cite{bsv} modules and the development of a bare-metal 
C benchmark suite. The work involves in-depth 
debugging of the Toooba memory subsystem, the design and evaluation of in-depth analyses of the FAT allocator and performance analysis at the instruction 
level. Alongside these technical efforts, the timeline reflects the structured drafting of academic publications and the ongoing development 
of the PhD thesis.

\begin{center}
\includegraphics[width=.9\linewidth]{./gnatt-chart.png}
\end{center}
\subsubsection{June to July 2025}
\label{sec:org2f8419d}
\begin{itemize}
\item Refactor BlueSpec SystemVerilog (BSV)\cite{bsv} modules within the CHERI Toooba architecture.
\item Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform.
\item Incorporate supervisory team feedback into revisions of the EuroSys paper.
\item Undertake formal progression review requirements.
\item Submit EuroSys paper to the CHERI research team at the University of Glasgow for preliminary feedback.
\end{itemize}
\subsubsection{July to August 2025}
\label{sec:org18e2368}
\begin{itemize}
\item Engage in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path.
\item Finalise and validate the C benchmark suite for the Toooba evaluation.
\item Begin technical documentation of the Toooba workflow, to support a 2nd publication.
\item Conclude revisions to the EuroSys paper by the end of July.
\end{itemize}
\subsubsection{August to September 2025}
\label{sec:org8f7cc7e}
\begin{itemize}
\item Continue debugging efforts within the Toooba memory subsystem.
\item Draft the abstract, introduction, and methodology sections of the second research paper.
\item Aim to generate preliminary experimental results for inclusion in the evaluation for the 2nd experiment.
\end{itemize}
\subsubsection{September to October 2025}
\label{sec:orgaeda479}
\begin{itemize}
\item Publish the EuroSys paper detailing the FAT-Pointer allocator.
\item Commence benchmarking of the Toooba design.
\item Simultaneously draft the evaluation and analysis sections of the 2nd paper.
\end{itemize}
\subsubsection{October to November 2025}
\label{sec:org5c3273b}
\begin{itemize}
\item Initiate 3rd experimental phase, aimed at deeper evaluation of prior experiments.
\item Modify memory allocators (TcMalloc and Mesh) to remove reliance on system `mmap` call.
\end{itemize}
\subsubsection{November to December 2025}
\label{sec:org3157e97}
\begin{itemize}
\item Finalise 2nd paper for peer review.
\item Strip away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh.
\item Analyse instruction-level reductions and performance implications.
\item Commence drafting of the 3rd research paper, building on contributions from the EuroSys paper.
\end{itemize}
\subsubsection{December 2025 to January 2026}
\label{sec:org0b82dc3}
\begin{itemize}
\item Conduct evaluation and profiling for the 3rd paper.
\item Commence thesis chapter write-up for Experiments 1 and 2.
\end{itemize}
\subsubsection{January to September 2026}
\label{sec:org1cc5f31}
\begin{itemize}
\item Continue thesis development and refinement across all experimental chapters.
\item Finalise and submitted 3rd paper for peer review.
\item Prepare complete PhD dissertation for submission.
\end{itemize}

\bibliographystyle{IEEEtran}
\bibliography{FuturePlan.bib}
\subsection{Appendix}
\label{sec:orgfc26bd9}
\subsection{(Experiment 3)Allocator evaluation based on stripping instruction calls for larger allocators}
\label{sec:orgae488c8}

\begin{figure}[htbp]
\centering
\includegraphics[width=.9\linewidth]{./memory_allocator.drawio.png}
\caption{\label{fig:org51a01ee}Deprecating the use of THP with CHERI bound aware embedded mmap.}
\end{figure}
\subsubsection{Box 1 (Transparent huge pages)}
\label{sec:org4622604}
The diagram \ref{fig:org51a01ee} highlights three specific implementations, the
first of which is the standard Transparent Huge Pages (THP)
mechanism employed by modern memory allocators. THP initially
focuses on handling smaller memory allocations. As the volume
of allocations increases, it employs a strategy that consolidates
these smaller allocations into contiguous memory regions.
Once aggregated, these regions are subsequently converted
into larger memory pages, typically of size 4MB, as seen
in allocators like jemalloc. This approach optimises memory
management by reducing fragmentation and improving performance
through the use of larger page sizes.

This approach, however, introduces additional
overhead, including the operations required to consolidate
smaller allocations and modify Translation Lookaside Buffer (TLB)
entries. These modifications can initially increase the
likelihood of TLB misses, as the process of grouping and
reorganizing memory allocations temporarily disrupts the
efficiency of TLB utilization. It is only after the
successful creation of the huge page that the benefits
materialize, leading to a reduction in TLB misses due
to the improved alignment of memory access patterns with
the larger page size.
\subsubsection{Box 2 (Our current implementation)}
\label{sec:org6f3a3db}
Box 2 outlines the current implementation, which involves the
pre-allocation of huge pages and leverages CHERI
(Capability Hardware Enhanced RISC Instructions) bounds
to meticulously track each allocation within these pages.
This approach enables a single TLB entry, combined with
the precise bounds defined by CHERI capabilities, to
facilitate block-based memory management within physically
contiguous regions. By enforcing strict bounds on pointers,
the system ensures that each pointer can only access memory
within its explicitly defined region.

Another critical aspect of this implementation is the
ability to define bounds of dynamic sizes, which stands
in contrast to traditional approaches that rely on
fixed-size page entries. Fixed-size entries inherently
require multiple TLB entries, regardless of the actual
memory usage, leading to inefficiencies. In the current
approach, when the allocated memory within a huge page
reaches its capacity, a new huge page is allocated.
However, a notable limitation of this method is its
dependence on the maximum huge page size supported by
the underlying processor architecture. In this case,
the system is constrained by the huge page size defined
by the CHERI-enhanced ARM v8.1\cite{noauthor_arm_nodate} architecture. While this
approach offers flexibility in memory allocation and
reduces the need for multiple TLB entries, it is
ultimately bounded by the hardware's architectural specifications.
\subsubsection{Box 3 (RISC-V implementation)}
\label{sec:org71d9f3b}
The third approach, as outlined in Box 3, deviates from the
use of huge pages and does not require memory to be
physically contiguous. In this model, each pointer
is designed to store comprehensive metadata at the pointer necessary
for the translation from virtual to physical addresses.
This metadata enables the system to manage memory allocations
without the constraints of physical contiguity, thereby
offering greater flexibility in memory utilization.
By embedding translation information directly within the
pointers, this approach eliminates the need for large,
contiguous memory regions and allows for more granular
and dynamic memory management.
\subsubsection{Building up from the work of Box 2 and Box 3 (Side effects we can strip away)}
\label{sec:org08d4ac7}
From a high-level perspective, the primary distinction between
Box 2 and Box 3 lies in the use of huge pages in the former
and their absence in the latter. Both approaches share
the common advantage of reducing the number of instructions
required in modern memory allocators by eliminating the
need for transitioning between smaller and larger pages.
This simplification streamlines memory management processes.
However, this document has not yet provided a detailed breakdown
or quantitative analysis of the specific performance implications
or trade-offs.

As illustrated to the right of the diagram, a sample snippet of
TC malloc from the paper "Beyond malloc Efficiency to Fleet
Efficiency"\cite{FleetAllocator} is provided. In the proposed approach, the entire
span function, which is essential in TC malloc, would become
unnecessary. Additionally, the approach offers the advantage
of simplifying memory management by integrating mmap directly
within the allocator. This integration eliminates the need for
separate mechanisms to handle memory mapping.
\subsubsection{Evaluation:}
\label{sec:org2a1bb59}
\begin{itemize}
\item The number of instructions that can be eliminated from a
page-aware memory allocator by adopting the proposed approach.

\item A comparative analysis of the memory allocator's performance
using wall-clock runtime measurements, both with and without
the modified mmap implementation.

\item While CHERI Purecap introduces additional instructions, such
as bounds checks, the overall approach aims to determine
whether it reduces the total number of instructions when
compared to a traditional ARMv8 Clang program using the
same allocator. This involves evaluating the trade-offs
between the overhead of CHERI-specific instructions and
the potential reductions in allocator-emitted instructions.
\end{itemize}
\end{document}