95 lines
5.4 KiB
TeX
95 lines
5.4 KiB
TeX
% Created 2025-01-20 Mon 13:33
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% Intended LaTeX compiler: pdflatex
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\documentclass[11pt]{article}
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\usepackage[utf8]{inputenc}
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\usepackage[T1]{fontenc}
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\usepackage{graphicx}
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\usepackage{longtable}
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\usepackage{wrapfig}
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\usepackage{rotating}
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\usepackage[normalem]{ulem}
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\usepackage{amsmath}
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\usepackage{amssymb}
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\usepackage{capt-of}
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\usepackage{hyperref}
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\author{Akilan}
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\date{\today}
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\title{}
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\hypersetup{
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pdfauthor={Akilan},
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pdftitle={},
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pdfkeywords={},
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pdfsubject={},
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pdfcreator={Emacs 29.1 (Org mode 9.6.6)},
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pdflang={English}}
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\begin{document}
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\tableofcontents
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\section{Introduction}
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\label{sec:org01b31aa}
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In computing, achieving high performance is an ongoing challenge, especially as
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applications handle increasingly complex workloads. Memory management is a key factor
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in performance, where efficient use of resources is essential. Translation Lookaside
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Buffers (TLBs) are crucial in this context, speeding up memory access by caching recent
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memory address translations. A TLB, a specialised cache in the memory management unit (MMU),
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reduces the time required to convert virtual addresses to physical ones. When a program accesses
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data in memory, the MMU first checks the TLB for a matching entry, avoiding the slower process of
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consulting page tables. However, as applications grow larger and more complex, the fixed size of
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TLBs often cannot keep up, leading to more TLB misses and performance slowdowns\cite{mittal_survey_2017}.
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To tackle this issue, researchers have explored new solutions, including the use of
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huge pages\cite{panwar_hawkeye_2019}.
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Huge pages, also known as large pages, allow for the allocation of memory in significantly larger chunks
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compared to traditional small pages. By reducing the number of TLB entries needed to access a given amount
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of memory, Huge pages offer a potential avenue for optimising TLB utilisation by reducing the number
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of entries needed to map large memory regions. This not only decreases the frequency of
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TLB misses but also lowers the overhead associated with address translation. By minimising
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these bottlenecks, huge pages can improve system performance in several ways, such as speeding
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up memory-intensive applications, reducing latency in data access, and enhancing throughput for
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workloads that rely heavily on large datasets.
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Simultaneously, advancements in hardware-level security, such as the Capability Hardware Enhanced RISC Instructions (CHERI)
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\cite{woodruff_cheri_2014} architecture, present additional opportunities for performance enhancement. CHERI's capability-based addressing approach not
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only strengthens system security by tightly controlling memory access but also opens avenues for optimising memory management
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operations. By integrating CHERI’s compressed\cite{woodruff_cheri_2019} encoded bounds with the use of huge pages, it becomes possible to track and manage
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large, physically contiguous memory blocks more efficiently. This combination reduces TLB pressure by minimising the number of
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entries required to map extensive memory regions, thereby decreasing TLB misses and improving address translation performance.
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Furthermore, it accelerates memory-intensive tasks by reducing the overhead associated with managing fragmented or non-contiguous
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memory allocations. The contributions for the following paper are as follows:
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\begin{itemize}
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\item \textbf{\textbf{Fat-pointer Based Range Addresses}}: Introduces fat-pointers that include memory bounds, allowing
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efficient tracking and management of physically contiguous memory regions.
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\item \textbf{\textbf{Custom Memory Allocation with Huge Pages}}: Proposes a custom `mmap` function and
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kernel module for allocating huge pages of physically contiguous memory, reducing the need for traditional
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TLB entries and improving efficiency.
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\item \textbf{\textbf{Novel Memory Allocation Algorithms}}: Provides new algorithms for allocating and freeing
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physically contiguous memory, integrating huge pages with CHERI’s capability-based bounds for enhanced memory management.
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\item \textbf{\textbf{CHERI’s Capability-based Optimization}}: Demonstrates how CHERI's architecture can be
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used to optimize memory allocation by encoding memory bounds directly within pointers, reducing TLB reliance.
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\end{itemize}
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Through comprehensive evaluation, including micro and macro benchmarks, we demonstrate the allocator’s ability
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to reduce TLB misses by up to 90\%, yielding significant improvements in wall clock runtimes for memory-intensive
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applications. While its impact on larger, computation-heavy workloads is less pronounced,
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the proposed allocator shows strong potential for advancing memory management in scenarios requiring
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high memory throughput and low translation overhead. The following below are research questions
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we are addressing:
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\begin{enumerate}
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\item How does the utilization of bounds for tracking memory allocations, in addition to security purposes, affect the
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run times and Translation Lookaside Buffer (TLB) miss rates in modern computing systems?
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\item How does the implementation of bounds for seeking through physically contiguous memory influence the complexity and
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efficiency of standard memory allocators, particularly those with advanced features such as transparent
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huge pages, and what are the implications for system performance in terms of execution speed, memory access
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latency, and resource utilization?
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\end{enumerate}
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\bibliographystyle{IEEEtran}
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\bibliography{introduction.bib}
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\end{document} |