51 lines
3.7 KiB
Python
51 lines
3.7 KiB
Python
import matplotlib.pyplot as plt
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import numpy as np
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# ypoints = np.array([19636392729, 9856229208,9445728437,5148906386])
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# xpoints = np.array([5,10,15,20])
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# ypoints1 = np.array([10062197042, 9873241615,12034929886,5118684853])
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# xpoints1 = np.array([5,10,15,20])
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ypoints = np.array(np.array([int(x) for x in """5527931
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8487180
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8358903
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8502471
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9044249
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4808340""".replace(' ',',').replace('\n','').split(",")]))
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xpoints = np.array([(i) for i, x in enumerate(ypoints, 1)])
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ypoints1 = np.array(np.array([int(x) for x in """4215408
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4561976
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4696311
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4662084
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4618990
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2799270""".replace(' ',',').replace('\n','').split(",")]))
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xpoints1 = np.array([(i) for i, x in enumerate(ypoints1, 1)])
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plt.plot(xpoints, ypoints,label='Malloc Physically contigous with bounds')
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plt.plot(xpoints1, ypoints1,label='System memory allocator')
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'''
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L1D_CACHE_LMISS_RD
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The counter counts each Memory-read operation to the Level 1 data or unified cache counted by L1D_CACHE that incurs additional latency because it returns data from outside of the Level 1 data or unified cache of this PE.
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The event indicates to software that the access missed in the Level 1 data or unified cache and might have a significant performance impact due to the additional latency compared to the latency of an access that hits in the Level 1 data or unified cache.
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The counter does not count:
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• Accesses where the additional latency is unlikely to be significantly performance-impacting. For example, if the access hits in another cache in the same local cluster, and the additional latency is small when compared to a miss in all Level 1 caches that the access looks up in and results in an access being made to a Level 2 cache or elsewhere beyond the Level 1 data or unified cache.
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• A miss that does not cause a new cache refill but is satisfied from a previous miss.
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An implementation is not required to measure the latency, nor to track the access to determine whether the additional latency caused a performance impact. An implementation can extend the definition of this event with additional scenarios where an access might have a significant performance impact due to additional latency for the access.
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It is IMPLEMENTATION DEFINED whether accesses that result from cache maintenance operations are counted.
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If the cache is shared and the Effective value of PMEVTYPER<n>_EL0.MT for the counter is 0, then the counter counts only events Attributable to the PE counting the event. For a multithreaded processor implementation, if the cache is shared by PEs other than the PEs in the multithreaded processor and the Effective value of PMEVTYPER<n>_EL0.MT for the counter is 1, then the counter counts only events Attributable to PEs in the multithreaded processor. In all other cases, it is IMPLEMENTATION DEFINED whether only events Attributable to the PE counting the event or all events are counted, and might depend on the Effective value of PMEVTYPER<n>_EL1.MT.
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PMCEID1_EL0[25] reads as 1 if this event is implemented and 0 otherwise. This event must be implemented if FEAT_PMUv3p4 is implemented.
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'''
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# plt.title("L1D cache miss read \n ARM Performance counter: L1D_CACHE_LMISS_RD \n each Memory-read operation or Memory-write operation that causes a cache \n access to at least the Level 1 data or unified cache. This includes each complete or partial translation table walk that causes an access to memory, including to data or translation table walk caches. \n Histogram large")
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plt.xlabel("time in seconds")
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plt.ylabel("LL cache miss")
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# plt.plot(xpoints1, ypoints1)
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plt.legend()
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# plt.show()
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plt.savefig('ll_cache_histogram_large.png') |