309 lines
14 KiB
TeX
309 lines
14 KiB
TeX
% Created 2025-06-23 Mon 16:58
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% Intended LaTeX compiler: pdflatex
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\documentclass[11pt]{article}
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\usepackage[utf8]{inputenc}
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\usepackage[T1]{fontenc}
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\usepackage{graphicx}
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\usepackage{longtable}
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\usepackage{wrapfig}
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\usepackage{rotating}
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\usepackage[normalem]{ulem}
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\usepackage{amsmath}
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\usepackage{amssymb}
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\usepackage{capt-of}
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\usepackage{hyperref}
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\author{Akilan}
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\date{\today}
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\title{}
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\hypersetup{
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pdfauthor={Akilan},
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pdftitle={},
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pdfkeywords={},
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pdfsubject={},
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pdfcreator={Emacs 30.1 (Org mode 9.7.11)},
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pdflang={English}}
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\begin{document}
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\tableofcontents
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\section{Plan}
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\label{sec:org0b4a538}
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This document outlines the proposed PhD research plan for the forthcoming academic year, building upon the outcomes and insights gained during the preceding year.
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\subsection{Current experiments:}
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\label{sec:org2ec96bb}
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\begin{itemize}
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\item (Experiment 1)FAT allocator with huge pages (EuroSys26 paper draft)
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\item (Experiment 2)FAT allocator to bypass TLB. (Proposal of ongoing expirement)
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\item (Experiment 3)Allocator evaluation based on stripping instruction calls from larger allocators. (Appendix)
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\end{itemize}
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\subsection{Experiment cancelled:}
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\label{sec:orgbfb4e3d}
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\begin{enumerate}
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\item Uni-Kernel Development (Reason): Work scaled down to fit within the allocated within PhD timeframe and instead introduced an extension of the FAT allocator as the third experiment.
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\end{enumerate}
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\subsection{Link to the Previous PhD Plan}
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\label{sec:org5e13e60}
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\begin{itemize}
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\item \url{https://github.com/Akilan1999/phd-thesis/releases/download/Year2/thesis.pdf}
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\end{itemize}
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\subsection{Summary of the Previous Plan}
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\label{sec:orgbef61d6}
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\subsubsection{Phase 1: FAT-Pointer Mechanism (July–September 2024)}
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\label{sec:orgc225731}
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\begin{enumerate}
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\item 1st to 15th July 2024
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\label{sec:orga23a507}
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\begin{itemize}
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\item Investigated causes of L1 TLB misses associated with contiguous memory allocation.
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\item Executed performance benchmarking using COZ\cite{coz} on selected C programs.
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\item Ported the kernel module to support SnMalloc, the default allocator in CheriBSD.
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\end{itemize}
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\item 15th to 30th July 2024
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\label{sec:orgdcdbfff}
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\begin{itemize}
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\item Conducted benchmarking using the SPEC and XSBench suites.
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\item Performed comparative analysis with both baseline and modified SnMalloc implementations.
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\end{itemize}
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\item August 2024
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\label{sec:org291b509}
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\begin{itemize}
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\item Initiated drafting of a paper for submission to EuroSys, focusing on the FAT-Pointer memory allocator (Current: On review stage).
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\end{itemize}
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\item September 2024
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\label{sec:org8e3adb1}
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\begin{itemize}
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\item Compiled and structured thesis chapter related to the FAT-Pointer architecture.
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\item Finalised and submitted the EuroSys paper.
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\end{itemize}
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\end{enumerate}
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\subsubsection{Phase 2: RISC-V Integration (October 2024 – May 2025)}
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\label{sec:orge4d0c50}
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\begin{enumerate}
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\item October to December 2024
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\label{sec:orge79764e}
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\begin{itemize}
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\item Modified the Bluespec implementation to enable TLB bypass in the memory access pipeline (Current: On progress).
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\item Configured the experimental platform and evaluation toolchain (Current: On progress).
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\end{itemize}
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\item January to February 2025
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\label{sec:orge05fc21}
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\begin{itemize}
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\item Undertook experimental evaluation of the FAT-Pointer system on RISC-V (Toooba) (Current: Todo).
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\item Commenced drafting of a technical paper for ISMM based on RISC-V integration results (Current: Todo).
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\end{itemize}
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\item March to May 2025
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\label{sec:org90e5eee}
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\begin{itemize}
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\item Addressed outstanding tasks and technical backlog.
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\item Continued development of the corresponding thesis chapter.
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\end{itemize}
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\end{enumerate}
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\subsubsection{Phase 3: Uni-Kernel Deployment (May 2025 – September 2026)}
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\label{sec:orgb30d702}
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\begin{enumerate}
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\item May to December 2025
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\label{sec:orgd428eea}
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\begin{itemize}
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\item Ported the memory allocator to a CHERI-enabled Uni-Kernel environment (Current: Cancelled)
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\item Designed and implemented a unified memory allocator to support both kernel and user-level allocations (Current: Cancelled)
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\item Initiated drafting of a manuscript targeted at OSDI (Current: Cancelled)
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\end{itemize}
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\item January to September 2026
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\label{sec:orga103287}
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\begin{itemize}
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\item Finalised documentation and submission of the PhD thesis (Current: New plan to still keep these dates unchanged)
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\item Submitted third research paper based on extended evaluation (Current: Replaced with "Allocator evaluation based on stripping instruction calls from larger allocators")
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\end{itemize}
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\end{enumerate}
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\subsection{Current Research Plan}
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\label{sec:org055ec33}
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This section outlines a comprehensive timeline of research activities and academic milestones to be undertaken between June
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2025 and September 2026 as part of the PhD to be focused on the CHERI Toooba architecture\cite{Toooba}. It includes the refactoring of BlueSpec\cite{bluespec} SystemVerilog\cite{bsv} modules and the development of a bare-metal
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C benchmark suite. The work involves in-depth
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debugging of the Toooba memory subsystem, the design and evaluation of in-depth analyses of the FAT allocator and performance analysis at the instruction
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level. Alongside these technical efforts, the timeline reflects the structured drafting of academic publications and the ongoing development
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of the PhD thesis.
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\begin{center}
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\includegraphics[width=.9\linewidth]{./gnatt-chart.png}
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\end{center}
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\subsubsection{June to July 2025}
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\label{sec:org2f8419d}
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\begin{itemize}
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\item Refactor BlueSpec SystemVerilog (BSV)\cite{bsv} modules within the CHERI Toooba architecture.
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\item Set up a bare-metal C benchmark suite for execution on the Bluespec simulation platform.
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\item Incorporate supervisory team feedback into revisions of the EuroSys paper.
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\item Undertake formal progression review requirements.
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\item Submit EuroSys paper to the CHERI research team at the University of Glasgow for preliminary feedback.
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\end{itemize}
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\subsubsection{July to August 2025}
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\label{sec:org18e2368}
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\begin{itemize}
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\item Engage in extensive debugging of the Toooba memory pipeline, specifically targeting the TLB bypass path.
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\item Finalise and validate the C benchmark suite for the Toooba evaluation.
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\item Begin technical documentation of the Toooba workflow, to support a 2nd publication.
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\item Conclude revisions to the EuroSys paper by the end of July.
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\end{itemize}
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\subsubsection{August to September 2025}
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\label{sec:org8f7cc7e}
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\begin{itemize}
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\item Continue debugging efforts within the Toooba memory subsystem.
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\item Draft the abstract, introduction, and methodology sections of the second research paper.
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\item Aim to generate preliminary experimental results for inclusion in the evaluation for the 2nd experiment.
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\end{itemize}
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\subsubsection{September to October 2025}
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\label{sec:orgaeda479}
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\begin{itemize}
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\item Publish the EuroSys paper detailing the FAT-Pointer allocator.
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\item Commence benchmarking of the Toooba design.
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\item Simultaneously draft the evaluation and analysis sections of the 2nd paper.
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\end{itemize}
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\subsubsection{October to November 2025}
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\label{sec:org5c3273b}
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\begin{itemize}
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\item Initiate 3rd experimental phase, aimed at deeper evaluation of prior experiments.
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\item Modify memory allocators (TcMalloc and Mesh) to remove reliance on system `mmap` call.
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\end{itemize}
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\subsubsection{November to December 2025}
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\label{sec:org3157e97}
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\begin{itemize}
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\item Finalise 2nd paper for peer review.
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\item Strip away huge-page-specific optimisations from JeMalloc, TcMalloc, and Mesh.
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\item Analyse instruction-level reductions and performance implications.
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\item Commence drafting of the 3rd research paper, building on contributions from the EuroSys paper.
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\end{itemize}
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\subsubsection{December 2025 to January 2026}
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\label{sec:org0b82dc3}
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\begin{itemize}
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\item Conduct evaluation and profiling for the 3rd paper.
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\item Commence thesis chapter write-up for Experiments 1 and 2.
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\end{itemize}
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\subsubsection{January to September 2026}
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\label{sec:org1cc5f31}
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\begin{itemize}
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\item Continue thesis development and refinement across all experimental chapters.
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\item Finalise and submitted 3rd paper for peer review.
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\item Prepare complete PhD dissertation for submission.
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\end{itemize}
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\bibliographystyle{IEEEtran}
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\bibliography{FuturePlan.bib}
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\subsection{Appendix}
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\label{sec:orgfc26bd9}
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\subsection{(Experiment 3)Allocator evaluation based on stripping instruction calls for larger allocators}
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\label{sec:orgae488c8}
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=.9\linewidth]{./memory_allocator.drawio.png}
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\caption{\label{fig:org51a01ee}Deprecating the use of THP with CHERI bound aware embedded mmap.}
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\end{figure}
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\subsubsection{Box 1 (Transparent huge pages)}
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\label{sec:org4622604}
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The diagram \ref{fig:org51a01ee} highlights three specific implementations, the
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first of which is the standard Transparent Huge Pages (THP)
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mechanism employed by modern memory allocators. THP initially
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focuses on handling smaller memory allocations. As the volume
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of allocations increases, it employs a strategy that consolidates
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these smaller allocations into contiguous memory regions.
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Once aggregated, these regions are subsequently converted
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into larger memory pages, typically of size 4MB, as seen
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in allocators like jemalloc. This approach optimises memory
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management by reducing fragmentation and improving performance
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through the use of larger page sizes.
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This approach, however, introduces additional
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overhead, including the operations required to consolidate
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smaller allocations and modify Translation Lookaside Buffer (TLB)
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entries. These modifications can initially increase the
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likelihood of TLB misses, as the process of grouping and
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reorganizing memory allocations temporarily disrupts the
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efficiency of TLB utilization. It is only after the
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successful creation of the huge page that the benefits
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materialize, leading to a reduction in TLB misses due
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to the improved alignment of memory access patterns with
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the larger page size.
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\subsubsection{Box 2 (Our current implementation)}
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\label{sec:org6f3a3db}
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Box 2 outlines the current implementation, which involves the
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pre-allocation of huge pages and leverages CHERI
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(Capability Hardware Enhanced RISC Instructions) bounds
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to meticulously track each allocation within these pages.
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This approach enables a single TLB entry, combined with
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the precise bounds defined by CHERI capabilities, to
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facilitate block-based memory management within physically
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contiguous regions. By enforcing strict bounds on pointers,
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the system ensures that each pointer can only access memory
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within its explicitly defined region.
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Another critical aspect of this implementation is the
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ability to define bounds of dynamic sizes, which stands
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in contrast to traditional approaches that rely on
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fixed-size page entries. Fixed-size entries inherently
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require multiple TLB entries, regardless of the actual
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memory usage, leading to inefficiencies. In the current
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approach, when the allocated memory within a huge page
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reaches its capacity, a new huge page is allocated.
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However, a notable limitation of this method is its
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dependence on the maximum huge page size supported by
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the underlying processor architecture. In this case,
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the system is constrained by the huge page size defined
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by the CHERI-enhanced ARM v8.1\cite{noauthor_arm_nodate} architecture. While this
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approach offers flexibility in memory allocation and
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reduces the need for multiple TLB entries, it is
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ultimately bounded by the hardware's architectural specifications.
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\subsubsection{Box 3 (RISC-V implementation)}
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\label{sec:org71d9f3b}
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The third approach, as outlined in Box 3, deviates from the
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use of huge pages and does not require memory to be
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physically contiguous. In this model, each pointer
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is designed to store comprehensive metadata at the pointer necessary
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for the translation from virtual to physical addresses.
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This metadata enables the system to manage memory allocations
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without the constraints of physical contiguity, thereby
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offering greater flexibility in memory utilization.
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By embedding translation information directly within the
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pointers, this approach eliminates the need for large,
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contiguous memory regions and allows for more granular
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and dynamic memory management.
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\subsubsection{Building up from the work of Box 2 and Box 3 (Side effects we can strip away)}
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\label{sec:org08d4ac7}
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From a high-level perspective, the primary distinction between
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Box 2 and Box 3 lies in the use of huge pages in the former
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and their absence in the latter. Both approaches share
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the common advantage of reducing the number of instructions
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required in modern memory allocators by eliminating the
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need for transitioning between smaller and larger pages.
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This simplification streamlines memory management processes.
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However, this document has not yet provided a detailed breakdown
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or quantitative analysis of the specific performance implications
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or trade-offs.
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As illustrated to the right of the diagram, a sample snippet of
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TC malloc from the paper "Beyond malloc Efficiency to Fleet
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Efficiency"\cite{FleetAllocator} is provided. In the proposed approach, the entire
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span function, which is essential in TC malloc, would become
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unnecessary. Additionally, the approach offers the advantage
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of simplifying memory management by integrating mmap directly
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within the allocator. This integration eliminates the need for
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separate mechanisms to handle memory mapping.
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\subsubsection{Evaluation:}
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\label{sec:org2a1bb59}
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\begin{itemize}
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\item The number of instructions that can be eliminated from a
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page-aware memory allocator by adopting the proposed approach.
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\item A comparative analysis of the memory allocator's performance
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using wall-clock runtime measurements, both with and without
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the modified mmap implementation.
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\item While CHERI Purecap introduces additional instructions, such
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as bounds checks, the overall approach aims to determine
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whether it reduces the total number of instructions when
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compared to a traditional ARMv8 Clang program using the
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same allocator. This involves evaluating the trade-offs
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between the overhead of CHERI-specific instructions and
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the potential reductions in allocator-emitted instructions.
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\end{itemize}
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\end{document}
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