113 lines
5.7 KiB
Plaintext
113 lines
5.7 KiB
Plaintext
; SPDX-License-Identifier: BSD-3-Clause
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; Copyright(c) 2010-2018 Intel Corporation
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; This setup demonstrates the usage of NIC Receive Side Scaling (RSS) feature.
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; Each NIC splits the input traffic into 4 RX queues, with each of its RX queues
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; being handled by a different pipeline:
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;
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; +-----------+ +----------+
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; +--------------------------->| | | |
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; | +------------------->| PIPELINE0 +--->| LINK 0 |--->
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; | | +------------->| (CORE A) | | TX |
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; | | | +------->| | | |
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; | | | | +-----------+ +----------+
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; +----------+ | | | |
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; | |-------+ | | |
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;--->| LINK 0 |-----------+ | | |
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; | RX |---------+ | | | |
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; | |-------+ | | | | |
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; +----------+ | | | | | | +-----------+ +----------+
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; | | +---|-----|-----|------->| | | |
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; +----------+ | | | +---|-----|------->| PIPELINE1 +--->| LINK 1 |--->
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; | |-------|-|-----+ | | +---|------->| (CORE B) | | TX |
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;--->| LINK 1 |-------|-|-------+ | | | +----->| | | |
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; | RX |-------|-|-------+ | | | | +-----------+ +----------+
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; | |-------|-|-----+ | | | | |
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; +----------+ | | | | | | | |
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; | | | | | | | |
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; +----------+ | | | | | | | |
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; | |-------|-|-----|-|---+ | | |
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;--->| LINK 2 |-------|-|-----|-|-----+ | | +-----------+ +----------+
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; | RX |-----+ | +-----|-|---------|-|----->| | | |
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; | |---+ | | | +---------|-|----->| PIPELINE2 +--->| LINK 2 |--->
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; +----------+ | +-|-------|-----------|-|----->| (CORE C) | | TX |
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; | | | | | +--->| | | |
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; +----------+ | | | | | | +-----------+ +----------+
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; | |---|---|-------|-----------+ | |
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;--->| LINK 3 |---|---|-------|-------------+ |
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; | RX |---|---|-------|---------------+
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; | |---|---|-------|-----------+
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; +----------+ | | | |
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; | | | | +-----------+ +----------+
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; | +-------|-----------|------->| | | |
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; | +-----------|------->| PIPELINE3 +--->| LINK 3 |--->
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; +-----------------------|------->| (CORE D) | | TX |
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; +------->| | | |
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; +-----------+ +----------+
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;
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;
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mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
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link LINK0 dev 0000:02:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
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link LINK1 dev 0000:02:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
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link LINK2 dev 0000:06:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
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link LINK3 dev 0000:06:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
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pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0
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pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0
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pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0
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pipeline PIPELINE0 table match stub
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pipeline PIPELINE0 port in 0 table 0
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pipeline PIPELINE0 port in 1 table 0
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pipeline PIPELINE0 port in 2 table 0
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pipeline PIPELINE0 port in 3 table 0
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pipeline PIPELINE0 table 0 rule add match default action fwd port 0
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pipeline PIPELINE1 period 10 offset_port_id 0 cpu 0
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pipeline PIPELINE1 port in bsz 32 link LINK0 rxq 1
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pipeline PIPELINE1 port in bsz 32 link LINK1 rxq 1
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pipeline PIPELINE1 port in bsz 32 link LINK2 rxq 1
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pipeline PIPELINE1 port in bsz 32 link LINK3 rxq 1
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pipeline PIPELINE1 port out bsz 32 link LINK1 txq 0
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pipeline PIPELINE1 table match stub
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pipeline PIPELINE1 port in 0 table 0
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pipeline PIPELINE1 port in 1 table 0
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pipeline PIPELINE1 port in 2 table 0
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pipeline PIPELINE1 port in 3 table 0
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pipeline PIPELINE1 table 0 rule add match default action fwd port 0
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pipeline PIPELINE2 period 10 offset_port_id 0 cpu 0
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pipeline PIPELINE2 port in bsz 32 link LINK0 rxq 2
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pipeline PIPELINE2 port in bsz 32 link LINK1 rxq 2
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pipeline PIPELINE2 port in bsz 32 link LINK2 rxq 2
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pipeline PIPELINE2 port in bsz 32 link LINK3 rxq 2
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pipeline PIPELINE2 port out bsz 32 link LINK2 txq 0
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pipeline PIPELINE2 table match stub
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pipeline PIPELINE2 port in 0 table 0
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pipeline PIPELINE2 port in 1 table 0
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pipeline PIPELINE2 port in 2 table 0
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pipeline PIPELINE2 port in 3 table 0
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pipeline PIPELINE2 table 0 rule add match default action fwd port 0
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pipeline PIPELINE3 period 10 offset_port_id 0 cpu 0
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pipeline PIPELINE3 port in bsz 32 link LINK0 rxq 3
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pipeline PIPELINE3 port in bsz 32 link LINK1 rxq 3
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pipeline PIPELINE3 port in bsz 32 link LINK2 rxq 3
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pipeline PIPELINE3 port in bsz 32 link LINK3 rxq 3
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pipeline PIPELINE3 port out bsz 32 link LINK3 txq 0
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pipeline PIPELINE3 table match stub
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pipeline PIPELINE3 port in 0 table 0
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pipeline PIPELINE3 port in 1 table 0
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pipeline PIPELINE3 port in 2 table 0
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pipeline PIPELINE3 port in 3 table 0
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pipeline PIPELINE3 table 0 rule add match default action fwd port 0
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thread 1 pipeline PIPELINE0 enable
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thread 2 pipeline PIPELINE1 enable
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thread 3 pipeline PIPELINE2 enable
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thread 4 pipeline PIPELINE3 enable
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