666 lines
56 KiB
BibTeX
666 lines
56 KiB
BibTeX
@article{TLBHierarchy,
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author = {Lustig, Daniel and Bhattacharjee, Abhishek and Martonosi, Margaret},
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title = {TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs},
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year = {2013},
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issue_date = {April 2013},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {10},
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number = {1},
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issn = {1544-3566},
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url = {https://doi.org/10.1145/2445572.2445574},
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doi = {10.1145/2445572.2445574},
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abstract = {Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as Chip MultiProcessors (CMPs) become ubiquitous, TLB design and performance must be reevaluated. Our article begins by performing a thorough TLB performance evaluation of sequential and parallel benchmarks running on a real-world, modern CMP system using hardware performance counters. This analysis demonstrates the need for further improvement of TLB hit rates for both classes of application, and it also points out that the data TLB has a significantly higher miss rate than the instruction TLB in both cases.In response to the characterization data, we propose and evaluate both Inter-Core Cooperative (ICC) TLB prefetchers and Shared Last-Level (SLL) TLBs as alternatives to the commercial norm of private, per-core L2 TLBs. ICC prefetchers eliminate 19\% to 90\% of Data TLB (D-TLB) misses across parallel workloads while requiring only modest changes in hardware. SLL TLBs eliminate 7\% to 79\% of D-TLB misses for parallel workloads and 35\% to 95\% of D-TLB misses for multiprogrammed sequential workloads. This corresponds to 27\% and 21\% increases in hit rates as compared to private, per-core L2 TLBs, respectively, and is achieved this using even more modest hardware requirements.Because of their benefits for parallel applications, their applicability to sequential workloads, and their readily implementable hardware, SLL TLBs and ICC TLB prefetchers hold great promise for CMPs.},
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journal = {ACM Trans. Archit. Code Optim.},
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month = apr,
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articleno = {2},
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numpages = {38},
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keywords = {TLB prefetching, Translation lookaside buffer, performance evaluation, shared last-level TLB, simulation}
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}
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@article{Shadow_superpages,
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title = {Aggressive superpage support with the shadow memory and the partial-subblock TLB},
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journal = {Microprocessors and Microsystems},
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volume = {25},
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number = {7},
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pages = {329-342},
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year = {2001},
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issn = {0141-9331},
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doi = {https://doi.org/10.1016/S0141-9331(01)00125-9},
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url = {https://www.sciencedirect.com/science/article/pii/S0141933101001259},
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author = {Cheol Ho Park and Daeyeon Park},
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keywords = {Superpage, Shadow memory, Subblock TLB, Translation lookaside buffer},
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abstract = {While superpages are an efficient solution to increase TLB reach, strong requirements for using superpages hinder the actual utilization. Two previous solutions, the partial-subblock TLB and the shadow memory were proposed to release the requirements. The partial-subblock TLB releases only a small portion of the requirements. The shadow memory releases most of the requirements but introduces other serious problems. We propose a hybrid scheme which integrates both the shadow memory and the partial-subblock TLB, thereby enjoying the benefits inherited from both sides. The hybrid scheme has as high a superpage utilization as the shadow memory, and avoids most of the problems in the shadow memory by virtue of the partial-subblock TLB. The experiment shows that the hybrid scheme outperforms the previous schemes though its hardware cost and overhead are considered.}
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}
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@article{THP,
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author = {Navarro, Juan and Iyer, Sitararn and Druschel, Peter and Cox, Alan},
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title = {Practical, transparent operating system support for superpages},
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year = {2003},
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issue_date = {Winter 2002},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {36},
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number = {SI},
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issn = {0163-5980},
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url = {https://doi.org/10.1145/844128.844138},
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doi = {10.1145/844128.844138},
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abstract = {Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a large physical memory region into a virtual address space. This dramatically increases TLB coverage, reduces TLB misses, and promises performance improvements for many applications. However, supporting superpages poses several challenges to the operating system, in terms of superpage allocation and promotion tradeoffs, fragmentation control, etc. We analyze these issues, and propose the design of an effective superpage management system. We implement it in FreeBSD on the Alpha CPU, and evaluate it on real workloads and benchmarks. We obtain substantial performance benefits, often exceeding 30\%; these benefits are sustained even under stressful workload scenarios.},
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journal = {SIGOPS Oper. Syst. Rev.},
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month = dec,
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pages = {89–104},
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numpages = {16}
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}
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@INPROCEEDINGS{TLBReach,
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author={Pham, Binh and Bhattacharjee, Abhishek and Eckert, Yasuko and Loh, Gabriel H.},
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booktitle={2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)},
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title={Increasing TLB reach by exploiting clustering in page translations},
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year={2014},
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volume={},
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number={},
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pages={558-567},
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keywords={Virtual private networks;Hardware;Organizations;Benchmark testing;Prefetching;Operating systems},
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doi={10.1109/HPCA.2014.6835964}
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}
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@article{DirectSegment,
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author = {Basu, Arkaprava and Gandhi, Jayneel and Chang, Jichuan and Hill, Mark D. and Swift, Michael M.},
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title = {Efficient virtual memory for big memory servers},
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year = {2013},
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issue_date = {June 2013},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {41},
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number = {3},
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issn = {0163-5964},
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url = {https://doi.org/10.1145/2508148.2485943},
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doi = {10.1145/2508148.2485943},
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abstract = {Our analysis shows that many "big-memory" server workloads, such as databases, in-memory caches, and graph analytics, pay a high cost for page-based virtual memory. They consume as much as 10\% of execution cycles on TLB misses, even using large pages. On the other hand, we find that these workloads use read-write permission on most pages, are provisioned not to swap, and rarely benefit from the full flexibility of page-based virtual memory.To remove the TLB miss overhead for big-memory workloads, we propose mapping part of a process's linear virtual address space with a direct segment, while page mapping the rest of the virtual address space. Direct segments use minimal hardware---base, limit and offset registers per core---to map contiguous virtual memory regions directly to contiguous physical memory. They eliminate the possibility of TLB misses for key data structures such as database buffer pools and in-memory key-value stores. Memory mapped by a direct segment may be converted back to paging when needed.We prototype direct-segment software support for x86-64 in Linux and emulate direct-segment hardware. For our workloads, direct segments eliminate almost all TLB misses and reduce the execution time wasted on TLB misses to less than 0.5\%.},
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journal = {SIGARCH Comput. Archit. News},
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month = jun,
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pages = {237–248},
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numpages = {12},
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keywords = {tanslation lookaside buffer, virtual memory}
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}
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@article{navarro_practical_nodate,
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title = {Practical, transparent operating system support for superpages},
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abstract = {Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer ({TLB}) to map a large physical memory region into a virtual address space. This dramatically increases {TLB} coverage, reduces {TLB} misses, and promises performance improvements for many applications. However, supporting superpages poses several challenges to the operating system, in terms of superpage allocation and promotion tradeoffs, fragmentation control, etc. We analyze these issues, and propose the design of an effective superpage management system. We implement it in {FreeBSD} on the Alpha {CPU}, and evaluate it on real workloads and benchmarks. We obtain substantial performance benefits, often exceeding 30\%; these benefits are sustained even under stressful workload scenarios.},
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author = {Navarro, Juan},
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langid = {english},
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file = {Navarro - Practical, transparent operating system support fo.pdf:/Users/akilan/Zotero/storage/9RBYAPGM/Navarro - Practical, transparent operating system support fo.pdf:application/pdf},
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}
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@inproceedings{panwar_hawkeye_2019,
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location = {Providence {RI} {USA}},
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title = {{HawkEye}: Efficient Fine-grained {OS} Support for Huge Pages},
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isbn = {978-1-4503-6240-5},
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url = {https://dl.acm.org/doi/10.1145/3297858.3304064},
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doi = {10.1145/3297858.3304064},
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shorttitle = {{HawkEye}},
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eventtitle = {{ASPLOS} '19: Architectural Support for Programming Languages and Operating Systems},
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pages = {347--360},
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booktitle = {Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems},
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publisher = {{ACM}},
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author = {Panwar, Ashish and Bansal, Sorav and Gopinath, K.},
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urldate = {2024-05-27},
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date = {2019-04-04},
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langid = {english},
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file = {Full Text PDF:/Users/akilan/Zotero/storage/VQLCKYCA/Panwar et al. - 2019 - HawkEye Efficient Fine-grained OS Support for Hug.pdf:application/pdf},
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}
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@inproceedings{karakostas_redundant_2015,
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location = {Portland Oregon},
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title = {Redundant memory mappings for fast access to large memories},
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isbn = {978-1-4503-3402-0},
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url = {https://dl.acm.org/doi/10.1145/2749469.2749471},
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doi = {10.1145/2749469.2749471},
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abstract = {Page-based virtual memory improves programmer productivity, security, and memory utilization, but incurs performance overheads due to costly page table walks after {TLB} misses. This overhead can reach 50\% for modern workloads that access increasingly vast memory with stagnating {TLB} sizes. To reduce the overhead of virtual memory, this paper proposes Redundant Memory Mappings ({RMM}), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. We define a range be a subset of process’s pages that are virtually and physically contiguous. {RMM} translates each range with a single range table entry, enabling a modest number of entries to translate most of the process’s address space. {RMM} operates in parallel with standard paging and uses a software range table and hardware range {TLB} with arbitrarily large reach. We modify the operating system to automatically detect ranges and to increase their likelihood with eager page allocation. {RMM} is thus transparent to applications. We prototype {RMM} software in Linux and emulate the hardware. {RMM} performs substantially better than paging alone and huge pages, and improves a wider variety of workloads than direct segments (one range per program), reducing the overhead of virtual memory to less than 1\% on average.},
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eventtitle = {{ISCA} '15: The 42nd Annual International Symposium on Computer Architecture},
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pages = {66--78},
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booktitle = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
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publisher = {{ACM}},
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author = {Karakostas, Vasileios and Gandhi, Jayneel and Ayar, Furkan and Cristal, Adrián and Hill, Mark D. and {McKinley}, Kathryn S. and Nemirovsky, Mario and Swift, Michael M. and Ünsal, Osman},
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urldate = {2024-05-27},
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date = {2015-06-13},
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langid = {english},
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file = {Karakostas et al. - 2015 - Redundant memory mappings for fast access to large.pdf:/Users/akilan/Zotero/storage/8JECES24/Karakostas et al. - 2015 - Redundant memory mappings for fast access to large.pdf:application/pdf},
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}
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@article{chen_flexpointer_2023,
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author = {Chen, Dongwei and Tong, Dong and Yang, Chun and Yi, Jiangfang and Cheng, Xu},
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title = {FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers},
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year = {2023},
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issue_date = {June 2023},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {20},
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number = {2},
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issn = {1544-3566},
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url = {https://doi.org/10.1145/3579854},
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doi = {10.1145/3579854},
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abstract = {Page-based virtual memory relies on TLBs to accelerate the address translation. Nowadays, the gap between application workloads and the capacity of TLB continues to grow, bringing many costly TLB misses and making the TLB a performance bottleneck. Previous studies seek to narrow the gap by exploiting the contiguity of physical pages. One promising solution is to group pages that are both virtually and physically contiguous into a memory range. Recording range translations can greatly increase the TLB reach, but ranges are also hard to index because they have arbitrary bounds. The processor has to compare against all the boundaries to determine which range an address falls in, which restricts the usage of memory ranges. In this article, we propose a tagged-pointer-based scheme, FlexPointer, to solve the range indexing problem. The core insight of FlexPointer is that large memory objects are rare, so we can create memory ranges based on such objects and assign each of them a unique ID. With the range ID integrated into pointers, we can index the range TLB with IDs and greatly simplify its structure. Moreover, because the ID is stored in the unused bits of a pointer and is not manipulated by the address generation, we can shift the range lookup to an earlier stage, working in parallel with the address generation. According to our trace-based simulation results, FlexPointer can reduce nearly all the L1 TLB misses, and page walks for a variety of memory-intensive workloads. Compared with a 4K-page baseline system, FlexPointer shows a 14\% performance improvement on average and up to 2.8x speedup in the best case. For other workloads, FlexPointer shows no performance degradation.},
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journal = {ACM Trans. Archit. Code Optim.},
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month = mar,
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articleno = {30},
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numpages = {24},
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keywords = {Tagged pointer, TLB reach, address translation}
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}
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@article{woodruff_cheri_2019,
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title = {{CHERI} Concentrate: Practical Compressed Capabilities},
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volume = {68},
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||
rights = {https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/{IEEE}.html},
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issn = {0018-9340, 1557-9956, 2326-3814},
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url = {https://ieeexplore.ieee.org/document/8703061/},
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doi = {10.1109/TC.2019.2914037},
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shorttitle = {{CHERI} Concentrate},
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abstract = {We present {CHERI} Concentrate, a new fat-pointer compression scheme applied to {CHERI}, the most developed capability-pointer system at present. Capability fat pointers are a primary candidate to enforce fine-grained and non-bypassable security properties in future computer systems, although increased pointer size can severely affect performance. Thus, several proposals for capability compression have been suggested elsewhere that do not support legacy instruction sets, ignore features critical to the existing software base, and also introduce design inefficiencies to {RISC}-style processor pipelines. {CHERI} Concentrate improves on the state-of-the-art region-encoding efficiency, solves important pipeline problems, and eases semantic restrictions of compressed encoding, allowing it to protect a full legacy software stack. We present the first quantitative analysis of compiled capability code, which we use to guide the design of the encoding format. We analyze and extend logic from the open-source {CHERI} prototype processor design on {FPGA} to demonstrate encoding efficiency, minimize delay of pointer arithmetic, and eliminate additional load-to-use delay. To verify correctness of our proposed high-performance logic, we present a {HOL}4 machine-checked proof of the decode and pointer-modify operations. Finally, we measure a 50\% to 75\% reduction in L2 misses for many compiled C-language benchmarks running under a commodity operating system using compressed 128-bit and 64-bit formats, demonstrating both compatibility with and increased performance over the uncompressed, 256-bit format.},
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pages = {1455--1469},
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number = {10},
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journaltitle = {{IEEE} Transactions on Computers},
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shortjournal = {{IEEE} Trans. Comput.},
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author = {Woodruff, Jonathan and Joannou, Alexandre and Xia, Hongyan and Fox, Anthony and Norton, Robert M. and Chisnall, David and Davis, Brooks and Gudka, Khilan and Filardo, Nathaniel W. and Markettos, A. Theodore and Roe, Michael and Neumann, Peter G. and Watson, Robert N. M. and Moore, Simon W.},
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urldate = {2024-05-27},
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date = {2019-10-01},
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langid = {english},
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file = {Woodruff et al. - 2019 - CHERI Concentrate Practical Compressed Capabiliti.pdf:/Users/akilan/Zotero/storage/3SZUIWQ5/Woodruff et al. - 2019 - CHERI Concentrate Practical Compressed Capabiliti.pdf:application/pdf},
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}
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@online{noauthor_capability-based_nodate,
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title = {Capability-Based Computer Systems},
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url = {https://homes.cs.washington.edu/~levy/capabook/},
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urldate = {2024-06-07},
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||
file = {Capability-Based Computer Systems:/Users/akilan/Zotero/storage/IAAG6ZF3/capabook.html:text/html},
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}
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@article{woodruff_cheri_2014,
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title = {The {CHERI} capability model: revisiting {RISC} in an age of risk},
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volume = {42},
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issn = {0163-5964},
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url = {https://doi.org/10.1145/2678373.2665740},
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doi = {10.1145/2678373.2665740},
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shorttitle = {The {CHERI} capability model},
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abstract = {Motivated by contemporary security challenges, we reevaluate and refine capability-based addressing for the {RISC} era. We present {CHERI}, a hybrid capability model that extends the 64-bit {MIPS} {ISA} with byte-granularity memory protection. We demonstrate that {CHERI} enables language memory model enforcement and fault isolation in hardware rather than software, and that the {CHERI} mechanisms are easily adopted by existing programs for efficient in-program memory safety. In contrast to past capability models, {CHERI} complements, rather than replaces, the ubiquitous page-based protection mechanism, providing a migration path towards deconflating data-structure protection and {OS} memory management. Furthermore, {CHERI} adheres to a strict {RISC} philosophy: it maintains a load-store architecture and requires only singlecycle instructions, and supplies protection primitives to the compiler, language runtime, and operating system. We demonstrate a mature {FPGA} implementation that runs the {FreeBSD} operating system with a full range of software and an open-source application suite compiled with an extended {LLVM} to use {CHERI} memory protection. A limit study compares published memory safety mechanisms in terms of instruction count and memory overheads. The study illustrates that {CHERI} is performance-competitive even while providing assurance and greater flexibility with simpler hardware},
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pages = {457--468},
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number = {3},
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journaltitle = {{ACM} {SIGARCH} Computer Architecture News},
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shortjournal = {{SIGARCH} Comput. Archit. News},
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author = {Woodruff, Jonathan and Watson, Robert N.M. and Chisnall, David and Moore, Simon W. and Anderson, Jonathan and Davis, Brooks and Laurie, Ben and Neumann, Peter G. and Norton, Robert and Roe, Michael},
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urldate = {2024-06-07},
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date = {2014-06-14},
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}
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@article{miller_towards_nodate,
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title = {Towards a Unified Approach to Access Control and Concurrency Control},
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author = {Miller, Mark Samuel},
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langid = {english},
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file = {Miller - Towards a Unified Approach to Access Control and Co.pdf:/Users/akilan/Zotero/storage/7METVAKG/Miller - Towards a Unified Approach to Access Control and Co.pdf:application/pdf},
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}
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@inproceedings{curtsinger_coz_2015,
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title = {Coz: Finding Code that Counts with Causal Profiling},
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url = {http://arxiv.org/abs/1608.03676},
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doi = {10.1145/2815400.2815409},
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shorttitle = {Coz},
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abstract = {Improving performance is a central concern for software developers. To locate optimization opportunities, developers rely on software profilers. However, these profilers only report where programs spent their time: optimizing that code may have no impact on performance. Past profilers thus both waste developer time and make it difficult for them to uncover significant optimization opportunities.},
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pages = {184--197},
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booktitle = {Proceedings of the 25th Symposium on Operating Systems Principles},
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author = {Curtsinger, Charlie and Berger, Emery D.},
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urldate = {2024-06-07},
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date = {2015-10-04},
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langid = {english},
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eprinttype = {arxiv},
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eprint = {1608.03676 [cs]},
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keywords = {C.4, Computer Science - Performance, D.4.8},
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file = {Curtsinger and Berger - 2015 - Coz Finding Code that Counts with Causal Profilin.pdf:/Users/akilan/Zotero/storage/QTFQXVHE/Curtsinger and Berger - 2015 - Coz Finding Code that Counts with Causal Profilin.pdf:application/pdf},
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||
}
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@online{noauthor_benchmark_nodate,
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title = {Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial},
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url = {https://www.cheribsd.org/tutorial/23.11/benchmark/index.html},
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howpublished = "\url{https://www.cheribsd.org/tutorial/23.11/benchmark/index.html}",
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||
urldate = {2024-06-07},
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||
file = {Benchmark ABI - CheriBSD 23.11 new features tutorial:/Users/akilan/Zotero/storage/9BDKUW28/index.html:text/html},
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||
}
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||
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||
@inproceedings{zhu_research_2018,
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||
location = {Taipei, Taiwan},
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title = {Research and Implementation of High Performance Traffic Processing Based on Intel {DPDK}},
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isbn = {978-1-5386-9403-9},
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||
url = {https://ieeexplore.ieee.org/document/8701793/},
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doi = {10.1109/PAAP.2018.00018},
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||
eventtitle = {2018 9th International Symposium on Parallel Architectures, Algorithms and Programming ({PAAP})},
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pages = {62--68},
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booktitle = {2018 9th International Symposium on Parallel Architectures, Algorithms and Programming ({PAAP})},
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publisher = {{IEEE}},
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author = {Zhu, Wenjun and Li, Peng and Luo, Baozhou and Xu, He and Zhang, Yujie},
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urldate = {2024-06-07},
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date = {2018-12},
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||
}
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@article{bi_dpdk-based_2016,
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title = {{DPDK}-based Improvement of Packet Forwarding},
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volume = {7},
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rights = {© Owned by the authors, published by {EDP} Sciences, 2016},
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issn = {2271-2097},
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url = {https://www.itm-conferences.org/articles/itmconf/abs/2016/02/itmconf_ita2016_01009/itmconf_ita2016_01009.html},
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doi = {10.1051/itmconf/20160701009},
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abstract = {Reel-time processing of packets occupies a significant position in the field of computer network security. With theexplosive growth of the backbone link rate,which is consistent with Gilder's law, many bottlenecks of server performance leave the real-time data stream unprocessed.Thus, we proposedto take use of {DPDK}(Data Plan Development Kit) framework to achieve an intelligent {NIC} packet forwarding system. During this research, we deeply analysis the forwarding process of packet in {DPDK} and improve its {DMA} mode.According to the results of experiment, the system greatly enhanced the performance of packet forwarding,and the throughput of forwarding 64-byet or random-length packets by 20Gbit {NIC} reaches13.3Gbps and 18.7Gbps(dual ports forwarding).},
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pages = {01009},
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journaltitle = {{ITM} Web of Conferences},
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shortjournal = {{ITM} Web Conf.},
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author = {Bi, Hao and Wang, Zhao-Hun},
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urldate = {2024-06-07},
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date = {2016},
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langid = {english},
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note = {Publisher: {EDP} Sciences},
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file = {Full Text PDF:/Users/akilan/Zotero/storage/LEVMJ983/Bi and Wang - 2016 - DPDK-based Improvement of Packet Forwarding.pdf:application/pdf},
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||
}
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||
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@article{esswood_cherios_nodate,
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title = {{CheriOS}: designing an untrusted single-address-space capability operating system utilising capability hardware and a minimal hypervisor},
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author = {Esswood, Lawrence G},
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langid = {english},
|
||
file = {Esswood - CheriOS designing an untrusted single-address-spa.pdf:/Users/akilan/Zotero/storage/YGIBFTD5/Esswood - CheriOS designing an untrusted single-address-spa.pdf:application/pdf},
|
||
}
|
||
|
||
@book{wilkes_cambridge_1979,
|
||
location = {New York},
|
||
title = {The Cambridge {CAP} computer and its operating system},
|
||
isbn = {978-0-444-00357-7 978-0-444-00358-4},
|
||
series = {The computer science library operating and programming systems series},
|
||
pagetotal = {165},
|
||
number = {6},
|
||
publisher = {North Holland},
|
||
author = {Wilkes, Maurice V. and Needham, Roger M.},
|
||
date = {1979},
|
||
langid = {english},
|
||
file = {Wilkes and Needham - 1979 - The Cambridge CAP computer and its operating syste.pdf:/Users/akilan/Zotero/storage/VIQTWZS3/Wilkes and Needham - 1979 - The Cambridge CAP computer and its operating syste.pdf:application/pdf},
|
||
}
|
||
|
||
@article{fillo_mmachine_nodate,
|
||
title = {The M–Machine Multicomputer},
|
||
author = {Fillo, Marco and Keckler, Stephen W and Dally, William J and Carter, Nicholas P and Chang, Andrew and Gurevich, Yevgeny and Lee, Whay S},
|
||
langid = {english},
|
||
file = {Fillo et al. - The M–Machine Multicomputer.pdf:/Users/akilan/Zotero/storage/LD95UQTM/Fillo et al. - The M–Machine Multicomputer.pdf:application/pdf},
|
||
}
|
||
|
||
@inproceedings{kwon_low-fat_2013,
|
||
location = {New York, {NY}, {USA}},
|
||
title = {Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security},
|
||
isbn = {978-1-4503-2477-9},
|
||
url = {https://dl.acm.org/doi/10.1145/2508859.2516713},
|
||
doi = {10.1145/2508859.2516713},
|
||
series = {{CCS} '13},
|
||
shorttitle = {Low-fat pointers},
|
||
abstract = {Referencing outside the bounds of an array or buffer is a common source of bugs and security vulnerabilities in today's software. We can enforce spatial safety and eliminate these violations by inseparably associating bounds with every pointer (fat pointer) and checking these bounds on every memory access. By further adding hardware-managed tags to the pointer, we make them unforgeable. This, in turn, allows the pointers to be used as capabilities to facilitate fine-grained access control and fast security domain crossing. Dedicated checking hardware runs in parallel with the processor's normal datapath so that the checks do not slow down processor operation (0\% runtime overhead). To achieve the safety of fat pointers without increasing program state, we compactly encode approximate base and bound pointers along with exact address pointers for a 46b address space into one 64-bit word with a worst-case memory overhead of 3\%. We develop gate-level implementations of the logic for updating and validating these compact fat pointers and show that the hardware requirements are low and the critical paths for common operations are smaller than processor {ALU} operations. Specifically, we show that the fat-pointer check and update operations can run in a 4 ns clock cycle on a Virtex 6 (40nm) implementation while only using 1100 6-{LUTs} or about the area of a double-precision, floating-point adder.},
|
||
pages = {721--732},
|
||
booktitle = {Proceedings of the 2013 {ACM} {SIGSAC} conference on Computer \& communications security},
|
||
publisher = {Association for Computing Machinery},
|
||
author = {Kwon, Albert and Dhawan, Udit and Smith, Jonathan M. and Knight, Thomas F. and {DeHon}, Andre},
|
||
urldate = {2024-06-18},
|
||
date = {2013-11-04},
|
||
keywords = {capabilities, fat pointer, memory safety, processor, security, spatial confinement},
|
||
file = {Full Text PDF:/Users/akilan/Zotero/storage/CVVZYZS4/Kwon et al. - 2013 - Low-fat pointers compact encoding and efficient g.pdf:application/pdf},
|
||
}
|
||
|
||
@article{wulf_hydra_1974,
|
||
title = {{HYDRA}: the kernel of a multiprocessor operating system},
|
||
volume = {17},
|
||
issn = {0001-0782, 1557-7317},
|
||
url = {https://dl.acm.org/doi/10.1145/355616.364017},
|
||
doi = {10.1145/355616.364017},
|
||
shorttitle = {{HYDRA}},
|
||
abstract = {This paper describes the design philosophy of {HYDRA}—the kernel of an operating system for C.mmp, the Carnegie-Mellon Multi-Mini-Processor. This philosophy is realized through the introduction of a generalized notion of “resource,” both physical and virtual, called an “object.” Mechanisms are presented for dealing with objects, including the creation of new types, specification of new operations applicable to a given type, sharing, and protection of any reference to a given object against improper application of any of the operations defined with respect to that type of object. The mechanisms provide a coherent basis for extension of the system in two directions: the introduction of new facilities, and the creation of highly secure systems.},
|
||
pages = {337--345},
|
||
number = {6},
|
||
journaltitle = {Communications of the {ACM}},
|
||
shortjournal = {Commun. {ACM}},
|
||
author = {Wulf, W. and Cohen, E. and Corwin, W. and Jones, A. and Levin, R. and Pierson, C. and Pollack, F.},
|
||
urldate = {2024-06-18},
|
||
date = {1974-06},
|
||
langid = {english},
|
||
file = {Full Text:/Users/akilan/Zotero/storage/EIRBNTVF/Wulf et al. - 1974 - HYDRA the kernel of a multiprocessor operating sy.pdf:application/pdf},
|
||
}
|
||
|
||
@article{hardy_keykos_1985,
|
||
title = {{KeyKOS} architecture},
|
||
volume = {19},
|
||
issn = {0163-5980},
|
||
url = {https://dl.acm.org/doi/10.1145/858336.858337},
|
||
doi = {10.1145/858336.858337},
|
||
pages = {8--25},
|
||
number = {4},
|
||
journaltitle = {{ACM} {SIGOPS} Operating Systems Review},
|
||
shortjournal = {{SIGOPS} Oper. Syst. Rev.},
|
||
author = {Hardy, Norman},
|
||
urldate = {2024-06-18},
|
||
date = {1985-10-01},
|
||
file = {Full Text PDF:/Users/akilan/Zotero/storage/QSYKM6QN/Hardy - 1985 - KeyKOS architecture.pdf:application/pdf},
|
||
}
|
||
|
||
@article{rashid_mach_nodate,
|
||
title = {Mach: A System Software Kernel},
|
||
abstract = {The Mach operating system can be used as a system software kernel which can support a variety of operating system environments. Key elements of the Mach design which allow it to efficiently support system software include integrated virtual memory management and interprocess communication, multiple threads of control within one address space, support for transparent system trap callout and an object programming facility integrated with the Mach {IPC} mechanisms. Mach is currently available both from {CMU} and commercially on a wide range of uniprocessor and multiprocessor hardware.},
|
||
author = {Rashid, Richard and Julin, Daniel and Orr, Douglas and Sanzi, Richard and Baron, Robert and Forin, Alessandro and Golub, David and Jones, Michael},
|
||
langid = {english},
|
||
file = {Rashid et al. - Mach A System Software Kernel.pdf:/Users/akilan/Zotero/storage/UHLILYH9/Rashid et al. - Mach A System Software Kernel.pdf:application/pdf},
|
||
}
|
||
|
||
@inproceedings{baumann_multikernel_2009,
|
||
location = {Big Sky Montana {USA}},
|
||
title = {The multikernel: a new {OS} architecture for scalable multicore systems},
|
||
isbn = {978-1-60558-752-3},
|
||
url = {https://dl.acm.org/doi/10.1145/1629575.1629579},
|
||
doi = {10.1145/1629575.1629579},
|
||
shorttitle = {The multikernel},
|
||
abstract = {Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instruction sets and variants, and {IO} configurations. Previous high-performance computing systems have scaled in specific cases, but the dynamic nature of modern client and server workloads, coupled with the impossibility of statically optimizing an {OS} for all workloads and hardware variants pose serious challenges for operating system structures.},
|
||
eventtitle = {{SOSP}09: {ACM} {SIGOPS} 22nd Symposium on Operating Systems Principles},
|
||
pages = {29--44},
|
||
booktitle = {Proceedings of the {ACM} {SIGOPS} 22nd symposium on Operating systems principles},
|
||
publisher = {{ACM}},
|
||
author = {Baumann, Andrew and Barham, Paul and Dagand, Pierre-Evariste and Harris, Tim and Isaacs, Rebecca and Peter, Simon and Roscoe, Timothy and Schüpbach, Adrian and Singhania, Akhilesh},
|
||
urldate = {2024-06-18},
|
||
date = {2009-10-11},
|
||
langid = {english},
|
||
file = {Baumann et al. - 2009 - The multikernel a new OS architecture for scalabl.pdf:/Users/akilan/Zotero/storage/4BVCRZN6/Baumann et al. - 2009 - The multikernel a new OS architecture for scalabl.pdf:application/pdf},
|
||
}
|
||
|
||
@article{watson_capsicum_nodate,
|
||
title = {Capsicum: practical capabilities for {UNIX}},
|
||
abstract = {Capsicum is a lightweight operating system capability and sandbox framework planned for inclusion in {FreeBSD} 9. Capsicum extends, rather than replaces, {UNIX} {APIs}, providing new kernel primitives (sandboxed capability mode and capabilities) and a userspace sandbox {API}. These tools support compartmentalisation of monolithic {UNIX} applications into logical applications, an increasingly common goal supported poorly by discretionary and mandatory access control. We demonstrate our approach by adapting core {FreeBSD} utilities and Google’s Chromium web browser to use Capsicum primitives, and compare the complexity and robustness of Capsicum with other sandboxing techniques.},
|
||
author = {Watson, Robert N M and Anderson, Jonathan and Kennaway, Kris and Laurie, Ben},
|
||
langid = {english},
|
||
file = {Watson et al. - Capsicum practical capabilities for UNIX.pdf:/Users/akilan/Zotero/storage/IAFXHJ8H/Watson et al. - Capsicum practical capabilities for UNIX.pdf:application/pdf},
|
||
}
|
||
|
||
@online{noauthor_department_nodate,
|
||
title = {Department of Computer Science and Technology: {CheriBSD}},
|
||
url = {https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheribsd.html},
|
||
urldate = {2024-06-18},
|
||
file = {Department of Computer Science and Technology\: CheriBSD:/Users/akilan/Zotero/storage/3XQJWCXD/cheribsd.html:text/html},
|
||
}
|
||
|
||
@online{noauthor_msrc-security-researchpapers2020security_nodate,
|
||
title = {{MSRC}-Security-Research/papers/2020/Security analysis of {CHERI} {ISA}.pdf at master · microsoft/{MSRC}-Security-Research},
|
||
url = {https://github.com/microsoft/MSRC-Security-Research/blob/master/papers/2020/Security%20analysis%20of%20CHERI%20ISA.pdf},
|
||
abstract = {Security Research from the Microsoft Security Response Center ({MSRC}) - microsoft/{MSRC}-Security-Research},
|
||
titleaddon = {{GitHub}},
|
||
urldate = {2024-06-18},
|
||
langid = {english},
|
||
file = {Snapshot:/Users/akilan/Zotero/storage/ENF2KYRT/Security analysis of CHERI ISA.html:text/html},
|
||
}
|
||
|
||
@inproceedings{zaliva_formal_2024,
|
||
location = {La Jolla {CA} {USA}},
|
||
title = {Formal Mechanised Semantics of {CHERI} C: Capabilities, Undefined Behaviour, and Provenance},
|
||
isbn = {9798400703720},
|
||
url = {https://dl.acm.org/doi/10.1145/3617232.3624859},
|
||
doi = {10.1145/3617232.3624859},
|
||
shorttitle = {Formal Mechanised Semantics of {CHERI} C},
|
||
abstract = {Memory safety issues are a persistent source of security vulnerabilities, with conventional architectures and the C codebase chronically prone to exploitable errors. The {CHERI} research project has shown how one can provide radically improved security for that existing codebase with minimal modification, using unforgeable hardware capabilities in place of machine-word pointers in {CHERI} dialects of C, implemented as adaptions of Clang/{LLVM} and {GCC}. {CHERI} was first prototyped as extensions of {MIPS} and {RISC}-V; it is currently being evaluated by Arm and others with the Arm Morello experimental architecture, processor, and platform, to explore its potential for mass-market adoption, and by Microsoft in their {CHERIoT} design for embedded cores.},
|
||
eventtitle = {{ASPLOS} '24: 29th {ACM} International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1},
|
||
pages = {181--196},
|
||
booktitle = {Proceedings of the 29th {ACM} International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1},
|
||
publisher = {{ACM}},
|
||
author = {Zaliva, Vadim and Memarian, Kayvan and Almeida, Ricardo and Clarke, Jessica and Davis, Brooks and Richardson, Alexander and Chisnall, David and Campbell, Brian and Stark, Ian and Watson, Robert N. M. and Sewell, Peter},
|
||
urldate = {2024-06-18},
|
||
date = {2024-04-27},
|
||
langid = {english},
|
||
file = {Zaliva et al. - 2024 - Formal Mechanised Semantics of CHERI C Capabiliti.pdf:/Users/akilan/Zotero/storage/8Y2CRHBS/Zaliva et al. - 2024 - Formal Mechanised Semantics of CHERI C Capabiliti.pdf:application/pdf},
|
||
}
|
||
|
||
@article{watson_cheri_nodate,
|
||
title = {{CHERI} C/C++ Programming Guide},
|
||
abstract = {This document is a brief introduction to the {CHERI} C/C++ programming languages. We explain the principles underlying these language variants, and their grounding in {CHERI}’s multiple architectural instantiations: {CHERI}-{MIPS}, {CHERI}-{RISC}-V, and Arm’s Morello. We describe the most commonly encountered differences between these dialects and C/C++ on conventional architectures, and where existing software may require minor changes. We document new compiler warnings and errors that may be experienced compiling code with the {CHERI} Clang/{LLVM} compiler, and suggest how they may be addressed through typically minor source-code changes. We explain how modest language extensions allow selected software, such as memory allocators, to further refine permissions and bounds on pointers. This guidance is based on our experience adapting the {FreeBSD} operating-system userspace, and applications such as {PostgreSQL} and {WebKit}, to run in a {CHERI} C/C++ capability-based programming environment. We conclude by recommending further reading.},
|
||
author = {Watson, Robert N M and Richardson, Alexander and Davis, Brooks and Baldwin, John and Chisnall, David and Clarke, Jessica and Filardo, Nathaniel and Moore, Simon W and Napierala, Edward and Sewell, Peter and Neumann, Peter G},
|
||
langid = {english},
|
||
file = {Watson et al. - CHERI CC++ Programming Guide.pdf:/Users/akilan/Zotero/storage/WHGQXE8P/Watson et al. - CHERI CC++ Programming Guide.pdf:application/pdf},
|
||
}
|
||
|
||
@article{esswood_cherios_nodate-1,
|
||
title = {{CheriOS}: designing an untrusted single-address-space capability operating system utilising capability hardware and a minimal hypervisor},
|
||
author = {Esswood, Lawrence G},
|
||
langid = {english},
|
||
file = {Esswood - CheriOS designing an untrusted single-address-spa.pdf:/Users/akilan/Zotero/storage/3IVKGYZ5/Esswood - CheriOS designing an untrusted single-address-spa.pdf:application/pdf},
|
||
}
|
||
|
||
@online{noauthor_architecture_nodate,
|
||
title = {The Architecture of the Burroughs B-5000},
|
||
url = {https://www.smecc.org/The%20Architecture%20%20of%20the%20Burroughs%20B-5000.htm},
|
||
urldate = {2024-06-18},
|
||
file = {The Architecture of the Burroughs B-5000:/Users/akilan/Zotero/storage/ELNL8VBQ/The Architecture of the Burroughs B-5000.html:text/html},
|
||
}
|
||
|
||
@article{dennis_programming_1966,
|
||
title = {Programming semantics for multiprogrammed computations},
|
||
volume = {9},
|
||
issn = {0001-0782, 1557-7317},
|
||
url = {https://dl.acm.org/doi/10.1145/365230.365252},
|
||
doi = {10.1145/365230.365252},
|
||
abstract = {The semantics are defined for a number of meta-instructions which perform operations essential to the writing of programs in multiprogrammed computer systems. These meta-instructions relate to parallel processing, protecting of separate computations, program debugging, and the sharing among users of memory segments and other computing objects, the names of which are hierarchically structured. The language sophistication contemplated is midway between an assembly language and an advanced algebraic language.},
|
||
pages = {143--155},
|
||
number = {3},
|
||
journaltitle = {Communications of the {ACM}},
|
||
shortjournal = {Commun. {ACM}},
|
||
author = {Dennis, Jack B. and Van Horn, Earl C.},
|
||
urldate = {2024-06-18},
|
||
date = {1966-03},
|
||
langid = {english},
|
||
file = {Full Text:/Users/akilan/Zotero/storage/6MLX2U8V/Dennis and Van Horn - 1966 - Programming semantics for multiprogrammed computat.pdf:application/pdf},
|
||
}
|
||
|
||
@article{watson_capability_nodate,
|
||
title = {Capability Hardware Enhanced {RISC} Instructions: {CHERI} Instruction-Set Architecture (Version 8)},
|
||
abstract = {This technical report describes {CHERI} {ISAv}8, the eighth version of the {CHERI} architecture being developed by {SRI} International and the University of Cambridge. This design captures ten years of research, development, experimentation, refinement, formal analysis, and validation through hardware and software implementation.},
|
||
author = {Watson, Robert N M and Neumann, Peter G and Woodruff, Jonathan and Roe, Michael and Almatary, Hesham and Anderson, Jonathan and Baldwin, John and Barnes, Graeme and Chisnall, David and Clarke, Jessica and Davis, Brooks and Eisen, Lee and Filardo, Nathaniel Wesley and Grisenthwaite, Richard and Joannou, Alexandre and Laurie, Ben and Markettos, A Theodore and Moore, Simon W and Murdoch, Steven J and Nienhuis, Kyndylan and Norton, Robert and Richardson, Alexander and Rugg, Peter and Sewell, Peter and Son, Stacey and Xia, Hongyan},
|
||
langid = {english},
|
||
file = {Watson et al. - Capability Hardware Enhanced RISC Instructions CH.pdf:/Users/akilan/Zotero/storage/R9T374YS/Watson et al. - Capability Hardware Enhanced RISC Instructions CH.pdf:application/pdf},
|
||
}
|
||
|
||
@online{noauthor_-it-yourself_nodate,
|
||
title = {Do-It-Yourself Virtual Memory Translation {\textbar} {ACM} {SIGARCH} Computer Architecture News},
|
||
url = {https://dl.acm.org/doi/10.1145/3140659.3080209},
|
||
urldate = {2024-06-18},
|
||
}
|
||
|
||
@online{noauthor_osdi_nodate,
|
||
title = {{OSDI} Symposia {\textbar} {USENIX}},
|
||
url = {https://www.usenix.org/conferences/byname/179},
|
||
urldate = {2024-06-19},
|
||
file = {OSDI Symposia | USENIX:/Users/akilan/Zotero/storage/VI7YCLJV/179.html:text/html},
|
||
}
|
||
|
||
@article{mittal_survey_2017,
|
||
title = {A survey of techniques for architecting {TLBs}},
|
||
volume = {29},
|
||
rights = {Copyright © 2016 John Wiley \& Sons, Ltd.},
|
||
issn = {1532-0634},
|
||
url = {https://onlinelibrary.wiley.com/doi/abs/10.1002/cpe.4061},
|
||
doi = {10.1002/cpe.4061},
|
||
abstract = {Translation lookaside buffer ({TLB}) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high-end servers. Because {TLB} is accessed very frequently and a {TLB} miss is extremely costly, prudent management of {TLB} is important for improving performance and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and managing {TLBs}. We characterize the techniques across several dimensions to highlight their similarities and distinctions. We believe that this paper will be useful for chip designers, computer architects, and system engineers.},
|
||
pages = {e4061},
|
||
number = {10},
|
||
journaltitle = {Concurrency and Computation: Practice and Experience},
|
||
author = {Mittal, Sparsh},
|
||
urldate = {2024-06-24},
|
||
date = {2017},
|
||
langid = {english},
|
||
note = {\_eprint: https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.4061},
|
||
keywords = {classification, power management, prefetching, Review, superpage, {TLB}, virtual cache, workload characterization},
|
||
file = {Snapshot:/Users/akilan/Zotero/storage/JJ9H6B2H/cpe.html:text/html},
|
||
}
|
||
|
||
@inproceedings{lietar_snmalloc_2019,
|
||
location = {New York, {NY}, {USA}},
|
||
title = {snmalloc: a message passing allocator},
|
||
isbn = {978-1-4503-6722-6},
|
||
url = {https://doi.org/10.1145/3315573.3329980},
|
||
doi = {10.1145/3315573.3329980},
|
||
series = {{ISMM} 2019},
|
||
shorttitle = {snmalloc},
|
||
abstract = {snmalloc is an implementation of malloc aimed at workloads in which objects are typically deallocated by a different thread than the one that had allocated them. We use the term producer/consumer for such workloads. snmalloc uses a novel message passing scheme which returns deallocated objects to the originating allocator in batches without taking any locks. It also uses a novel bump pointer-free list data structure with which just 64-bits of meta-data are sufficient for each 64 {KiB} slab. On such producer/consumer benchmarks our approach performs better than existing allocators. Snmalloc is available at {\textless}a href="https://github.com/Microsoft/snmalloc"{\textgreater}https://github.com/Microsoft/snmalloc{\textless}/a{\textgreater}.},
|
||
pages = {122--135},
|
||
booktitle = {Proceedings of the 2019 {ACM} {SIGPLAN} International Symposium on Memory Management},
|
||
publisher = {Association for Computing Machinery},
|
||
author = {Liétar, Paul and Butler, Theodore and Clebsch, Sylvan and Drossopoulou, Sophia and Franco, Juliana and Parkinson, Matthew J. and Shamis, Alex and Wintersteiger, Christoph M. and Chisnall, David},
|
||
urldate = {2024-06-23},
|
||
date = {2019-06-23},
|
||
keywords = {Memory allocation, message passing},
|
||
}
|
||
|
||
@online{cheribsd,
|
||
title = {Benchmark {ABI} - {CheriBSD} 23.11 new features tutorial},
|
||
url = {https://www.cheribsd.org/tutorial/23.11/benchmark/index.html},
|
||
urldate = {2024-06-07},
|
||
file = {Benchmark ABI - CheriBSD 23.11 new features tutorial:/Users/akilan/Zotero/storage/9BDKUW28/index.html:text/html},
|
||
}
|
||
|
||
@TechReport{BenchmarkABI,
|
||
author = {Watson, Robert N. M. and Clarke, Jessica and Sewell, Peter
|
||
and Woodruff, Jonathan and Moore, Simon W. and Barnes,
|
||
Graeme and Grisenthwaite, Richard and Stacer, Kathryn and
|
||
Baranga, Silviu and Richardson, Alexander},
|
||
title = {{Early performance results from the prototype Morello
|
||
microarchitecture}},
|
||
institution = {University of Cambridge, Computer Laboratory},
|
||
address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom,
|
||
phone +44 1223 763500},
|
||
month = {September},
|
||
year = {2023},
|
||
number = {UCAM-CL-TR-986}
|
||
}
|
||
|
||
@inproceedings{jemalloc,
|
||
title={A scalable concurrent malloc (3) implementation for FreeBSD},
|
||
author={Evans, Jason},
|
||
booktitle={Proc. of the bsdcan conference, ottawa, canada},
|
||
year={2006}
|
||
}
|
||
|
||
@online{Benchmark,
|
||
title = {{CHERI}-Allocator/benchmarks/benchmarks/{StressTestMalloc}/glibc-bench.c at main · Akilan1999/{CHERI}-Allocator},
|
||
url = {https://github.com/Akilan1999/CHERI-Allocator/blob/main/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c},
|
||
urldate = {2025-01-15},
|
||
file = {CHERI-Allocator/benchmarks/benchmarks/StressTestMalloc/glibc-bench.c at main · Akilan1999/CHERI-Allocator:/Users/akilan/Zotero/storage/2X8ZJLND/glibc-bench.html:text/html},
|
||
}
|
||
|
||
@online{Morello,
|
||
title = {Department of Computer Science and Technology – {CHERI}: The Arm Morello Board},
|
||
url = {https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello.html},
|
||
urldate = {2025-01-16},
|
||
file = {Department of Computer Science and Technology – CHERI\: The Arm Morello Board:/Users/akilan/Zotero/storage/GCMNX8LY/cheri-morello.html:text/html},
|
||
}
|
||
|
||
@online{PerformanceCounter,
|
||
title = {Arm Architecture Reference Manual for A-profile architecture},
|
||
url = {https://developer.arm.com/documentation/ddi0487/latest},
|
||
urldate = {2025-01-15},
|
||
file = {Arm Architecture Reference Manual for A-profile architecture:/Users/akilan/Zotero/storage/BVZSP7HA/latest.html:text/html},
|
||
}
|
||
|
||
@article{TLBBehavoir,
|
||
author = {Kandiraju, Gokul B. and Sivasubramaniam, Anand},
|
||
title = {Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks},
|
||
year = {2002},
|
||
issue_date = {June 2002},
|
||
publisher = {Association for Computing Machinery},
|
||
address = {New York, NY, USA},
|
||
volume = {30},
|
||
number = {1},
|
||
issn = {0163-5999},
|
||
url = {https://doi.org/10.1145/511399.511351},
|
||
doi = {10.1145/511399.511351},
|
||
abstract = {Despite the numerous optimization and evaluation studies that have been conducted with TLBs over the years, there is still a deficiency in an indepth understanding of TLB characteristics from an application angle. This paper presents a detailed characterization study of the TLB behavior of the SPEC CPU2000 benchmark suite. The contributions of this work are in identifying important application characteristics for TLB studies, quantifying the SPEC2000 application behavior for these characteristics, as well as making pronouncements and suggestions for future research based on these results.Around one-fourth of the SPEC2000 applications (ammp, apsi, galgel, lucas, mcf, twolf and vpr) have significant TLB missrates. Both capacity and associativity are influencing factors on miss-rates, though they do not necessarily go hand-in-hand. Multi-level TLBs are definitely useful for these applications in cutting down access times without significant miss rate degradation. Superpaging to combine TLB entries may not be rewarding for many of these applications. Software management of TLBs in terms of determining what entries to prefetch, what entries to replace, and what entries to pin has a lot of potential to cut down miss rates considerably. Specifically, the potential benefits of prefetching TLB entries is examined, and Distance Prefetching is shown to give good prediction accuracy for these applications.},
|
||
journal = {SIGMETRICS Perform. Eval. Rev.},
|
||
month = jun,
|
||
pages = {129–139},
|
||
numpages = {11}
|
||
}
|
||
|
||
@inproceedings{IntelItanium,
|
||
author = {Cornea, Marius and Harrison, John and Tang, Ping Tak Peter},
|
||
title = {Intel® Itanium® floating-point architecture},
|
||
year = {2003},
|
||
isbn = {9781450347327},
|
||
publisher = {Association for Computing Machinery},
|
||
address = {New York, NY, USA},
|
||
url = {https://doi.org/10.1145/1275521.1275526},
|
||
doi = {10.1145/1275521.1275526},
|
||
abstract = {The Intel® Itanium® architecture is increasingly becoming one of the major processor architectures present in the market today. Launched in 2001, the Intel Itanium processor was followed in 2002 by the Itanium 2 processor, with increased integer and floating-point performance. Measured by the SPEC CINT2000 benchmarks, the Itanium 2 processor still trails by about 25\% the Intel P4 processor in integer performance, albeit P4 runs at more than three times Itanium's clock frequency. However, its floating-point performance clearly leads in the SPEC CFP2000 charts, and its rating is about 25\% higher than that of the P4 processor. While the general features of the Itanium architecture such as large register sets, predication, speculation, and support for explicit parallelism [1] have been presented in several papers, books, and mainstream college textbooks [2], its floating-point architecture has been less publicized. Two books, [3] and [4], cover well this area. The present paper focuses on the floating-point architecture of the Itanium processor family, and points out a few remarkable features suitable to be the focus of a lecture, lab session, or project in a computer architecture class.},
|
||
booktitle = {Proceedings of the 2003 Workshop on Computer Architecture Education: Held in Conjunction with the 30th International Symposium on Computer Architecture},
|
||
pages = {3–es},
|
||
location = {San Diego, California},
|
||
series = {WCAE '03}
|
||
}
|
||
|
||
@phdthesis{singh1993,
|
||
author = {Singh, Jaswinder Pal},
|
||
title = {Parallel Hierarchical N-body Methods and Their Implications for Multiprocessors},
|
||
school = {Stanford University},
|
||
year = {1993},
|
||
month = feb,
|
||
}
|
||
|
||
@article{holt1995,
|
||
author = {Singh, Jaswinder Pal and Hennessy, John L. and Gupta, Anoop},
|
||
title = {Implications of hierarchical N-body methods for multiprocessor architectures},
|
||
year = {1995},
|
||
issue_date = {May 1995},
|
||
publisher = {Association for Computing Machinery},
|
||
address = {New York, NY, USA},
|
||
volume = {13},
|
||
number = {2},
|
||
issn = {0734-2071},
|
||
url = {https://doi.org/10.1145/201045.201050},
|
||
doi = {10.1145/201045.201050},
|
||
abstract = {To design effective large-scale multiprocessors, designers need to understand the characteristics of the applications that will use the machines. Application characteristics of particular interest include the amount of communication relative to computation, the structure of the communication, and the local cache and memory requirements, as well as how these characteristics scale with larger problems and machines. One important class of applications is based on hierarchical N-body methods, which are used to solve a wide range of scientific and engineering problems efficiently. Important characteristics of these methods include the nonuniform and dynamically changing nature of the domains to which they are applied, and their use of long-range, irregular communication. This article examines the key architectural implications of representative applications that use the two dominant hierarchical N-body methods: the Barnes-Hut Method and the Fast Multipole Method.We first show that exploiting temporal locality on accesses to communicated data is critical to obtaining good performance on these applications and then argue that coherent caches on shared-address-space machines exploit this locality both automatically and very effectively. Next, we examine the implications of scaling the applications to run on larger machines. We use scaling methods that reflect the concerns of the application scientist and find that this leads to different conclusions about how communication traffic and local cache and memory usage scale than scaling based only on data set size. In particular, we show that under the most realistic form of scaling, both the communication-to-computation ratio as well as the working-set size (and hence the ideal cache size per processor) grow slowly as larger problems are run on larger machines. Finally, we examine the effects of using the two dominant abstractions for interprocessor communication: a shared address space and explicit message passing between private address spaces. We show that the lack of an efficiently supported shared address space will substantially increase the programming complexity and performance overheads for these applications.},
|
||
journal = {ACM Trans. Comput. Syst.},
|
||
month = may,
|
||
pages = {141–202},
|
||
numpages = {62},
|
||
keywords = {N-body methods, communication abstractions, locality, message passing, parallel applications, parallel computer architecture, scaling, shared address space, shared memory}
|
||
}
|
||
|
||
@article{evans_scalable_nodate,
|
||
title = {A {Scalable} {Concurrent} malloc(3) {Implementation} for {FreeBSD}},
|
||
abstract = {The FreeBSD project has been engaged in ongoing work to provide scalable support for multi-processor computer systems since version 5. Sufficient progress has been made that the C library’s malloc(3) memory allocator is now a potential bottleneck for multi-threaded applications running on multiprocessor systems. In this paper, I present a new memory allocator that builds on the state of the art to provide scalable concurrent allocation for applications. Benchmarks indicate that with this allocator, memory allocation for multi-threaded applications scales well as the number of processors increases. At the same time, single-threaded allocation performance is similar to the previous allocator implementation.},
|
||
language = {en},
|
||
author = {Evans, Jason},
|
||
file = {Evans - A Scalable Concurrent malloc(3) Implementation for.pdf:/Users/akilan/Zotero/storage/4ZE7JS5V/Evans - A Scalable Concurrent malloc(3) Implementation for.pdf:application/pdf},
|
||
}
|
||
|
||
@inproceedings{CheriABI,
|
||
author = {Davis, Brooks and Watson, Robert N. M. and Richardson, Alexander and Neumann, Peter G. and Moore, Simon W. and Baldwin, John and Chisnall, David and Clarke, Jessica and Filardo, Nathaniel Wesley and Gudka, Khilan and Joannou, Alexandre and Laurie, Ben and Markettos, A. Theodore and Maste, J. Edward and Mazzinghi, Alfredo and Napierala, Edward Tomasz and Norton, Robert M. and Roe, Michael and Sewell, Peter and Son, Stacey and Woodruff, Jonathan},
|
||
title = {CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment},
|
||
year = {2019},
|
||
isbn = {9781450362405},
|
||
publisher = {Association for Computing Machinery},
|
||
address = {New York, NY, USA},
|
||
url = {https://doi.org/10.1145/3297858.3304042},
|
||
doi = {10.1145/3297858.3304042},
|
||
abstract = {The CHERI architecture allows pointers to be implemented as capabilities (rather than integer virtual addresses) in a manner that is compatible with, and strengthens, the semantics of the C language. In addition to the spatial protections offered by conventional fat pointers, CHERI capabilities offer strong integrity, enforced provenance validity, and access monotonicity. The stronger guarantees of these architectural capabilities must be reconciled with the real-world behavior of operating systems, run-time environments, and applications. When the process model, user-kernel interactions, dynamic linking, and memory management are all considered, we observe that simple derivation of architectural capabilities is insufficient to describe appropriate access to memory. We bridge this conceptual gap with a notional abstract capability that describes the accesses that should be allowed at a given point in execution, whether in the kernel or userspace. To investigate this notion at scale, we describe the first adaptation of a full C-language operating system (FreeBSD) with an enterprise database (PostgreSQL) for complete spatial and referential memory safety. We show that awareness of abstract capabilities, coupled with CHERI architectural capabilities, can provide more complete protection, strong compatibility, and acceptable performance overhead compared with the pre-CHERI baseline and software-only approaches. Our observations also have potentially significant implications for other mitigation techniques.},
|
||
booktitle = {Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems},
|
||
pages = {379–393},
|
||
numpages = {15},
|
||
keywords = {cheri, hardware, operating systems, security},
|
||
location = {Providence, RI, USA},
|
||
series = {ASPLOS '19}
|
||
}
|
||
|
||
@inproceedings{XSBench,
|
||
author = {Tramm, John R and Siegel, Andrew R and Islam, Tanzima and Schulz, Martin},
|
||
title = {{XSBench} - The Development and Verification of a Performance Abstraction for {M}onte {C}arlo Reactor Analysis},
|
||
booktitle = {{PHYSOR} 2014 - The Role of Reactor Physics toward a Sustainable Future},
|
||
address = {Kyoto},
|
||
year = 2014,
|
||
url = "https://www.mcs.anl.gov/papers/P5064-0114.pdf"
|
||
}
|
||
|
||
|
||
|