108 lines
3.7 KiB
TeX
108 lines
3.7 KiB
TeX
% Created 2025-02-22 Sat 16:07
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% Intended LaTeX compiler: pdflatex
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\documentclass[11pt]{article}
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\usepackage[utf8]{inputenc}
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\usepackage[T1]{fontenc}
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\usepackage{graphicx}
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\usepackage{longtable}
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\usepackage{wrapfig}
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\usepackage{rotating}
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\usepackage[normalem]{ulem}
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\usepackage{amsmath}
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\usepackage{amssymb}
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\usepackage{capt-of}
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\usepackage{hyperref}
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\author{Akilan}
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\date{\today}
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\title{}
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\hypersetup{
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pdfauthor={Akilan},
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pdftitle={},
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pdfkeywords={},
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pdfsubject={},
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pdfcreator={Emacs 29.4 (Org mode 9.6.15)},
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pdflang={English}}
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\begin{document}
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\tableofcontents
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\section{Future work}
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\label{sec:org9893feb}
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This documents is decision making to highlight
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potential paths to take for this PhD.
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We will initially talk about the current expirement
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which is a FAT pointer based memory allocator
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and will then expand into 2 potential paths:
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\begin{itemize}
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\item Cheri RISCV to prevent using the TLB.
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\item Allocator evaluation based on stripping instruction
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calls for larger allocators like Jemalloc.
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\end{itemize}
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\subsection{Current expirement: FAT pointer based range addresses}
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\label{sec:org538d2a3}
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\begin{itemize}
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\item TODO add diagram
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\end{itemize}
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The objective of this expirement was to ensure we can use the CHERI bounds as
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tracking mechanism of allocations instead of using multiple TLB entries. Using
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this approach we can use a single Huge page entry with bounds to ensure that
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the bounds (Which is the top and base address) can be extracted from the
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pointer using the Cheri compressed bounds mechanism. We implemented a simple
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allocator which uses this technique with a basic malloc and free.
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\subsubsection{Objectives (Todo steal research questions from the paper)}
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\label{sec:org4ffe05f}
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\begin{itemize}
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\item Reduce the number of TLB walks (Reducing each transaltion to 2 CPU CYCLES with huge pages).
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\item Using a block based style allocations inside huge pages.
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\end{itemize}
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\subsubsection{Hardware}
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\label{sec:orgee1de56}
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\begin{itemize}
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\item ARM morello (Huge page size 1GB used)
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\end{itemize}
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\subsubsection{Evaluation (Steal evaluation from the paper)}
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\label{sec:orgc7e36f5}
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\subsubsection{limitation}
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\label{sec:org1f89017}
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\begin{itemize}
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\item Using Huge page still requires a TLB entry which could be mitigated
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(Refer to the FPGA work).
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\item ARMv8 only supports using to virtual addresses so it's required to
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bypass the TLB for address translation.
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\end{itemize}
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\subsection{Cheri RISCV to prevent using the TLB}
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\label{sec:org81619f5}
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In the current ARM Morello setup, address
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translations rely on the TLB. The future approach
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on RISC-V Tooba involves storing the offset directly within the pointer.
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This is possible due to CHERI’s capability model, which supports
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fine-grained memory protection and can encode bounds within pointers.
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Utilizing Bounds in CHERI for Block-Based Allocation:
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CHERI capabilities allow pointers to carry metadata about memory bounds,
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providing hardware-enforced memory safety. By encoding the offset
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and bounds within the pointer, the system can directly access memory
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without needing intermediate translations via the TLB. This enables the
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implementation of a block-based allocator that can efficiently manage memory
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allocations and deallocations within defined bounds. Bypassing the TLB in RISC-V Tooba.
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\subsubsection{Hardware modifications}
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\label{sec:orgc0b3d36}
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The Bluespec design of the RISC-V processor will be modified to allow
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certain memory operations to bypass the TLB. This means that when a pointer
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with encoded offset and bounds is used, the system can directly compute the
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physical address from the capability information. This modification reduces the
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dependency on the TLB, decreasing latency.
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and improving performance, especially for frequent memory operations.
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\end{document}
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