64 lines
5.6 KiB
BibTeX
64 lines
5.6 KiB
BibTeX
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@article{woodruff_cheri_2019,
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title = {{CHERI} {Concentrate}: {Practical} {Compressed} {Capabilities}},
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volume = {68},
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copyright = {https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html},
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issn = {0018-9340, 1557-9956, 2326-3814},
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shorttitle = {{CHERI} {Concentrate}},
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url = {https://ieeexplore.ieee.org/document/8703061/},
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doi = {10.1109/TC.2019.2914037},
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abstract = {We present CHERI Concentrate, a new fat-pointer compression scheme applied to CHERI, the most developed capability-pointer system at present. Capability fat pointers are a primary candidate to enforce fine-grained and non-bypassable security properties in future computer systems, although increased pointer size can severely affect performance. Thus, several proposals for capability compression have been suggested elsewhere that do not support legacy instruction sets, ignore features critical to the existing software base, and also introduce design inefficiencies to RISC-style processor pipelines. CHERI Concentrate improves on the state-of-the-art region-encoding efficiency, solves important pipeline problems, and eases semantic restrictions of compressed encoding, allowing it to protect a full legacy software stack. We present the first quantitative analysis of compiled capability code, which we use to guide the design of the encoding format. We analyze and extend logic from the open-source CHERI prototype processor design on FPGA to demonstrate encoding efficiency, minimize delay of pointer arithmetic, and eliminate additional load-to-use delay. To verify correctness of our proposed high-performance logic, we present a HOL4 machine-checked proof of the decode and pointer-modify operations. Finally, we measure a 50\% to 75\% reduction in L2 misses for many compiled C-language benchmarks running under a commodity operating system using compressed 128-bit and 64-bit formats, demonstrating both compatibility with and increased performance over the uncompressed, 256-bit format.},
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language = {en},
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number = {10},
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urldate = {2024-05-27},
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journal = {IEEE Transactions on Computers},
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author = {Woodruff, Jonathan and Joannou, Alexandre and Xia, Hongyan and Fox, Anthony and Norton, Robert M. and Chisnall, David and Davis, Brooks and Gudka, Khilan and Filardo, Nathaniel W. and Markettos, A. Theodore and Roe, Michael and Neumann, Peter G. and Watson, Robert N. M. and Moore, Simon W.},
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month = oct,
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year = {2019},
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pages = {1455--1469},
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file = {Woodruff et al. - 2019 - CHERI Concentrate Practical Compressed Capabiliti.pdf:/Users/akilan/Zotero/storage/3SZUIWQ5/Woodruff et al. - 2019 - CHERI Concentrate Practical Compressed Capabiliti.pdf:application/pdf},
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}
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@misc{noauthor_jemalloc_nodate,
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title = {{JEMALLOC}},
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url = {https://jemalloc.net/jemalloc.3.html},
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urldate = {2025-01-15},
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file = {JEMALLOC:/Users/akilan/Zotero/storage/QDEIEJ9N/jemalloc.3.html:text/html},
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}
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@misc{noauthor_arm_nodate,
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title = {Arm {Architecture} {Reference} {Manual} for {A}-profile architecture},
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url = {https://developer.arm.com/documentation/ddi0487/latest},
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urldate = {2025-01-15},
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file = {Arm Architecture Reference Manual for A-profile architecture:/Users/akilan/Zotero/storage/BVZSP7HA/latest.html:text/html},
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}
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@misc{noauthor_department_nodate,
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title = {Department of {Computer} {Science} and {Technology} – {CHERI}: {The} {Arm} {Morello} {Board}},
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url = {https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello.html},
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urldate = {2025-01-16},
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file = {Department of Computer Science and Technology – CHERI\: The Arm Morello Board:/Users/akilan/Zotero/storage/GCMNX8LY/cheri-morello.html:text/html},
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}
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@article{navarro_practical_nodate,
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title = {Practical, transparent operating system support for superpages},
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abstract = {Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a large physical memory region into a virtual address space. This dramatically increases TLB coverage, reduces TLB misses, and promises performance improvements for many applications. However, supporting superpages poses several challenges to the operating system, in terms of superpage allocation and promotion tradeoffs, fragmentation control, etc. We analyze these issues, and propose the design of an effective superpage management system. We implement it in FreeBSD on the Alpha CPU, and evaluate it on real workloads and benchmarks. We obtain substantial performance benefits, often exceeding 30\%; these benefits are sustained even under stressful workload scenarios.},
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language = {en},
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author = {Navarro, Juan},
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file = {Navarro - Practical, transparent operating system support fo.pdf:/Users/akilan/Zotero/storage/R9MSCWQX/Navarro - Practical, transparent operating system support fo.pdf:application/pdf},
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}
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@misc{noauthor_ctsrd-cheritoooba_nodate,
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title = {{CTSRD}-{CHERI}/{Toooba}: {RISC}-{V} {Core}; superscalar, out-of-order, multi-core capable; based on {RISCY}-{OOO} from {MIT}},
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url = {https://github.com/CTSRD-CHERI/Toooba},
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urldate = {2025-02-25},
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file = {CTSRD-CHERI/Toooba\: RISC-V Core\; superscalar, out-of-order, multi-core capable\; based on RISCY-OOO from MIT:/Users/akilan/Zotero/storage/BQPSL2D6/Toooba.html:text/html},
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}
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@article{witaszczyk_pure-capability_nodate,
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title = {Pure-capability third-party software for {Arm} {Morello} and {CHERI}-{RISC}-{V} {CheriBSD}},
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language = {en},
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author = {Witaszczyk, Konrad},
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file = {Witaszczyk - Pure-capability third-party software for Arm Morel.pdf:/Users/akilan/Zotero/storage/549XSPL6/Witaszczyk - Pure-capability third-party software for Arm Morel.pdf:application/pdf},
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}
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