284 lines
12 KiB
TeX
284 lines
12 KiB
TeX
% Created 2025-02-26 Wed 15:30
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% Intended LaTeX compiler: pdflatex
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\documentclass[11pt]{article}
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\usepackage[utf8]{inputenc}
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\usepackage[T1]{fontenc}
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\usepackage{graphicx}
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\usepackage{longtable}
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\usepackage{wrapfig}
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\usepackage{rotating}
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\usepackage[normalem]{ulem}
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\usepackage{amsmath}
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\usepackage{amssymb}
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\usepackage{capt-of}
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\usepackage{hyperref}
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\setcounter{secnumdepth}{0}
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\author{Akilan}
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\date{\today}
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\title{}
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\hypersetup{
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pdfauthor={Akilan},
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pdftitle={},
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pdfkeywords={},
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pdfsubject={},
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pdfcreator={Emacs 29.4 (Org mode 9.6.15)},
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pdflang={English}}
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\begin{document}
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\tableofcontents
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\section*{Future work}
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\label{sec:orgda47b6e}
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This documents is decision making to highlight
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potential paths to take for this PhD.
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We will initially talk about the current expirement
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which is a FAT pointer based memory allocator
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and will then expand into 2 potential paths:
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\begin{itemize}
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\item Cheri RISCV to prevent using the TLB.
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\item Allocator evaluation based on stripping instruction
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calls for larger allocators like Jemalloc\cite{noauthor_jemalloc_nodate}.
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\end{itemize}
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\subsection*{1. Current expirement: FAT pointer based range addresses}
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\label{sec:org3d72d8f}
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=.9\linewidth]{./HighOverviewArchitecture.drawio.png}
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\caption{\label{fig:orgcd7570b}FAT pointer implementation with Huge pages against a standard malloc allocator.}
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\end{figure}
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The objective of this expirement was to ensure we can use the CHERI bounds as
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tracking mechanism of allocations instead of using multiple TLB entries. Using
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this approach we can use a single Huge page\cite{navarro_practical_nodate} entry with bounds to ensure that
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the bounds (Which is the top and base address) can be extracted from the
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pointer using the Cheri compressed bounds\cite{woodruff_cheri_2019} mechanism. We implemented a simple
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allocator which uses this technique with a basic malloc and free.
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\subsubsection*{Objectives}
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\label{sec:org9153cb3}
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\begin{itemize}
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\item How does the utilization of bounds for tracking memory
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allocations, in addition to security purposes, affect
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the run times and Translation Lookaside Buffer (TLB)
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miss rates in modern computing systems ?
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\item How does the implementation of bounds for seeking through
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physically contiguous memory influence the complexity and
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efficiency of standard memory allocators, particularly
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those with advanced features such as transparent huge pages,
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and what are the implications for system performance in terms
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of execution speed, memory access latency, and resource
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utilization?
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\end{itemize}
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\subsubsection*{Hardware}
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\label{sec:orgd94c91f}
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\begin{itemize}
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\item ARM morello\cite{noauthor_department_nodate} (Huge page size 1GB used)
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\end{itemize}
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\subsubsection*{Evaluation}
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\label{sec:orgc8016e9}
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We conducted tests of the FAT Pointer-based range addresses against Jemalloc,
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the default memory allocator for CHERIBSD, to assess the
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performance improvements enabled by a CHERI-based huge page-aware
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alocator. Specifically, we evaluated the reduction in TLB misses
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and its impact on overall performance metrics, such as wall clock runtime.
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To comprehensively analyze the proposed allocator,
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we categorized benchmarks into two classes which are micro and
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macro benchmarks. Micro benchmarks comprise smaller C programs
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designed to target specific allocator patterns, enabling us
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to evaluate detailed aspects of the allocator’s behavior.
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Macro benchmarks, on the other hand, encompass larger,
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realworld C programs, allowing us to assess the allocator’s
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performance in more practical, real-world scenarios.
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\subsubsection*{limitation}
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\label{sec:orgec3f8c5}
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\begin{itemize}
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\item Using Huge page still requires a TLB entry which could be mitigated
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(Refer to the FPGA work).
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\item ARMv8 only supports using to virtual addresses so it's required to
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bypass the TLB for address translation.
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\end{itemize}
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\subsection*{2. Cheri RISCV to prevent using the TLB}
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\label{sec:org54690ae}
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=200px]{./MainOverview.png}
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\caption{\label{fig:org7fecd7d}FAT pointer implementation with RISCV CHERI Toooba to strip the requirement of requiring a TLB.}
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\end{figure}
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In the current ARM Morello setup, address
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translations rely on the TLB. The future approach
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on RISC-V Tooba\cite{noauthor_ctsrd-cheritoooba_nodate} involves storing the offset directly within the pointer.
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This is possible due to CHERI’s capability model, which supports
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fine-grained memory protection and can encode bounds within pointers.
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Utilizing Bounds in CHERI for Block-Based Allocation:
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CHERI capabilities allow pointers to carry metadata about memory bounds,
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providing hardware-enforced memory safety. By encoding the offset
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and bounds within the pointer, the system can directly access memory
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without needing intermediate translations via the TLB. This enables the
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implementation of a block-based allocator that can efficiently manage memory
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allocations and deallocations within defined bounds. Bypassing the TLB in RISC-V Tooba.
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\subsubsection*{Hardware modifications}
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\label{sec:orgc9c424e}
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The Bluespec design of the RISC-V processor will be modified to allow
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certain memory operations to bypass the TLB. This means that when a pointer
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with encoded offset and bounds is used, the system can directly compute the
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physical address from the capability information. This modification reduces the
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dependency on the TLB, decreasing latency.
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and improving performance, especially for frequent memory operations.
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\subsection*{3. Allocator evaluation based on stripping instruction calls for larger allocators}
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\label{sec:org50ff3ae}
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=.9\linewidth]{./memory_allocator.drawio.png}
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\caption{\label{fig:org71f4ddc}Deprecating the use of THP with CHERI bound aware embedded mmap.}
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\end{figure}
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\subsubsection*{Box 1 (Transparent huge pages)}
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\label{sec:orgcd7e5f0}
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The diagram \ref{fig:org71f4ddc} highlights three specific implementations, the
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first of which is the standard Transparent Huge Pages (THP)
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mechanism employed by modern memory allocators. THP initially
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focuses on handling smaller memory allocations. As the volume
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of allocations increases, it employs a strategy that consolidates
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these smaller allocations into contiguous memory regions.
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Once aggregated, these regions are subsequently converted
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into larger memory pages, typically of size 4MB, as seen
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in allocators like jemalloc. This approach optimizes memory
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management by reducing fragmentation and improving performance
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through the use of larger page sizes.
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This approach, however, introduces additional
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overhead, including the operations required to consolidate
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smaller allocations and modify Translation Lookaside Buffer (TLB)
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entries. These modifications can initially increase the
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likelihood of TLB misses, as the process of grouping and
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reorganizing memory allocations temporarily disrupts the
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efficiency of TLB utilization. It is only after the
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successful creation of the huge page that the benefits
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materialize, leading to a reduction in TLB misses due
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to the improved alignment of memory access patterns with
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the larger page size.
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\subsubsection*{Box 2 (Our current implementation)}
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\label{sec:org41ee7a8}
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Box 2 outlines the current implementation, which involves the
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pre-allocation of huge pages and leverages CHERI
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(Capability Hardware Enhanced RISC Instructions) bounds
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to meticulously track each allocation within these pages.
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This approach enables a single TLB entry, combined with
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the precise bounds defined by CHERI capabilities, to
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facilitate block-based memory management within physically
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contiguous regions. By enforcing strict bounds on pointers,
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the system ensures that each pointer can only access memory
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within its explicitly defined region.
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Another critical aspect of this implementation is the
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ability to define bounds of dynamic sizes, which stands
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in contrast to traditional approaches that rely on
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fixed-size page entries. Fixed-size entries inherently
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require multiple TLB entries, regardless of the actual
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memory usage, leading to inefficiencies. In the current
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approach, when the allocated memory within a huge page
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reaches its capacity, a new huge page is allocated.
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However, a notable limitation of this method is its
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dependence on the maximum huge page size supported by
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the underlying processor architecture. In this case,
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the system is constrained by the huge page size defined
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by the CHERI-enhanced ARM v8.1\cite{noauthor_arm_nodate} architecture. While this
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approach offers flexibility in memory allocation and
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reduces the need for multiple TLB entries, it is
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ultimately bounded by the hardware's architectural specifications.
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\subsubsection*{Box 3 (RISC-V implementation)}
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\label{sec:org9f9a21d}
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The third approach, as outlined in Box 3, deviates from the
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use of huge pages and does not require memory to be
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physically contiguous. In this model, each pointer
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is designed to store comprehensive metadata at the pointer necessary
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for the translation from virtual to physical addresses.
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This metadata enables the system to manage memory allocations
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without the constraints of physical contiguity, thereby
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offering greater flexibility in memory utilization.
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By embedding translation information directly within the
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pointers, this approach eliminates the need for large,
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contiguous memory regions and allows for more granular
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and dynamic memory management.
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\subsubsection*{Building up from the work of Box 2 and Box 3 (Side effects we can strip away)}
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\label{sec:org3dac27a}
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From a high-level perspective, the primary distinction between
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Box 2 and Box 3 lies in the use of huge pages in the former
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and their absence in the latter. Both approaches share
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the common advantage of reducing the number of instructions
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required in modern memory allocators by eliminating the
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need for transitioning between smaller and larger pages.
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This simplification streamlines memory management processes.
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However, this document has not yet provided a detailed breakdown
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or quantitative analysis of the specific performance implications
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or trade-offs.
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As illustrated to the right of the diagram, a sample snippet of
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TC malloc from the paper Beyond malloc Efficiency to Fleet
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Efficiency is provided. In the proposed approach, the entire
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span function, which is essential in TC malloc, would become
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unnecessary. Additionally, the approach offers the advantage
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of simplifying memory management by integrating mmap directly
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within the allocator. This integration eliminates the need for
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separate mechanisms to handle memory mapping.
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\subsubsection*{Evaluation:}
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\label{sec:org84b9699}
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\begin{itemize}
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\item The number of instructions that can be eliminated from a
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page-aware memory allocator by adopting the proposed approach.
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\item A comparative analysis of the memory allocator's performance
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using wall-clock runtime measurements, both with and without
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the modified mmap implementation.
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\item While CHERI Purecap introduces additional instructions, such
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as bounds checks, the overall approach aims to determine
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whether it reduces the total number of instructions when
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compared to a traditional ARMv8 Clang program using the
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same allocator. This involves evaluating the trade-offs
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between the overhead of CHERI-specific instructions and
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the potential reductions in allocator-emitted instructions.
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\end{itemize}
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\subsection*{Current tasks on hand}
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\label{sec:org3fd32dc}
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\begin{enumerate}
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\item To port over all chapters written to a
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EuroSys Conferenece document and send over the
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to the supervisory team for a review.
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\begin{itemize}
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\item This will then get send over to Jeremy
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for an external review.
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\item Expands to a talk in the University
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of Glasgow seminar.
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\item Concurrent suggestions of the Eurosys
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submission till may.
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\end{itemize}
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\item Work on allocator evaluation based on stripping instruction calls for
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larger allocators (Expirement agreed in the meeting).
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\item Write to Cambridge a proposal for using the RISC-V expirement (2 weeks).
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\end{enumerate}
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\bibliographystyle{IEEEtran}
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\bibliography{FuturePlan.bib}
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\end{document}
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