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FAT-Allocator/docs/RISCV-FAT/Paper/diagram.tex
2025-06-18 18:05:10 +01:00

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\documentclass{article}
\usepackage{algorithm}
\usepackage{algpseudocode}
\usepackage{amsmath}
\begin{document}
\begin{algorithm}
\caption{Modified Memory Pipeline Stages}
\begin{algorithmic}[1]
\Procedure{\textbf{doDispatchMem}}{}
\State Enqueue into \texttt{regToExeQ}:
\State \quad \texttt{mem\_func} $\gets x.\texttt{mem\_func}$
\State \quad \texttt{imm} $\gets x.\texttt{imm}$
\State \quad \texttt{tag} $\gets x.\texttt{tag}$
\State \dots
\State \quad \texttt{rVal1}, \texttt{rVal2}, \texttt{vaddr}, \texttt{cap\_checks}, \texttt{origBE}, \texttt{shiftBEData}
\State \dots
\State \quad \texttt{spec\_bits} $\gets \texttt{dispToReg.spec\_bits}$
\EndProcedure
\Statex
\Procedure{\textbf{doExeMem}}{}
\State \texttt{regToExe} $\gets$ \texttt{regToExeQ.first}
\State \texttt{regToExeQ.deq()}
\State \dots
\State \texttt{shiftBE} $\gets$ DataMemAccess(\texttt{x.shiftBEData})
\If{\texttt{x.origBE == TagMemAccess}}
\State \texttt{shiftBE} $\gets$ TagMemAccess
\EndIf
\State \texttt{ddc} $\gets$ cast(\texttt{inIfc.scaprf\_rd(scrAddrDDC)})
\State Compute \texttt{accessByteCount}
\If{\texttt{x.origBE == TagMemAccess}}
\State \texttt{accessByteCount} $\gets$ \texttt{CLineNumMemDataBytes}
\EndIf
\State \dots
\textbf{\State Call procPAddr(x.vaddr)}
\EndProcedure
\Statex
\Procedure{\textbf{doFinishMem}}{}
\State \dots
\State \texttt{PAddrResp} $\gets$ \texttt{procPAddr.procResp}
\State \texttt{x} $\gets$ \texttt{PAddrResp.inst}
\State \{\texttt{paddr}, \texttt{expCause}, \texttt{allowCapPTE}\} $\gets$ \texttt{PAddrResp.resp}
\State \texttt{cause} $\gets$ Invalid
\If{\texttt{expCause} matches Valid \texttt{c}}
\State \texttt{cause} $\gets$ Valid(Exception(\texttt{c}))
\EndIf
\State \dots
\EndProcedure
\end{algorithmic}
\end{algorithm}
\end{document}