482 lines
30 KiB
HTML
482 lines
30 KiB
HTML
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</head>
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<body>
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<div id="content" class="content">
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<div id="table-of-contents" role="doc-toc">
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<h2>Table of Contents</h2>
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<div id="text-table-of-contents" role="doc-toc">
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<ul>
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<li><a href="#org490606f">1. Evaluation</a>
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<ul>
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<li><a href="#org2f83090">1.1. Expirement setup</a>
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<ul>
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<li><a href="#org0d440d4">1.1.1. Performance counters used</a></li>
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<li><a href="#org9cacc1c">1.1.2. Benchmarks</a></li>
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</ul>
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</li>
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<li><a href="#orgcc0820e">1.2. Results</a></li>
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<li><a href="#org1d8ebaa">1.3. Usability</a></li>
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</ul>
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</li>
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</ul>
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</div>
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</div>
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<div id="outline-container-org490606f" class="outline-2">
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<h2 id="org490606f"><span class="section-number-2">1.</span> Evaluation</h2>
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<div class="outline-text-2" id="text-1">
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<p>
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We conducted tests of the FAT Pointer-based range addresses against Jemalloc,
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the default memory allocator for CHERIBSD(, ), to assess the performance improvements
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enabled by a CHERI-based huge page-aware allocator. Specifically, we evaluated
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the reduction in TLB misses and its impact on overall
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performance metrics, such as wall clock runtime.
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</p>
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<p>
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To comprehensively analyze the proposed allocator, we categorized benchmarks into
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two classes which are micro and macro benchmarks. Micro benchmarks comprise smaller
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C programs designed to target specific allocator patterns, enabling us to evaluate
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detailed aspects of the allocator's behavior. Macro benchmarks, on the other hand,
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encompass larger, real-world C programs, allowing us to assess the allocator's
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performance in more practical, real-world scenarios.
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</p>
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<p>
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The experiment setup details the software stack used for evaluation. It includes
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the specific configurations, compiler options, and system environment tailored
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to benchmark the proposed allocator. This ensures consistency and repeatability
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in our results, providing a solid foundation for meaningful comparisons.
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</p>
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<p>
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We further elaborated on the two classes of benchmarks executed. Micro benchmarks
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focused on particular allocation and deallocation patterns, such as sequential and
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random memory accesses, to stress-test the allocator under controlled conditions.
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Macro benchmarks involved real-world applications, offering insights into how
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the allocator performs with complex memory allocation demands, large datasets,
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and varying execution contexts.
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</p>
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<p>
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The results section presents the outcomes of our benchmarks, highlighting key metrics
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such as TLB miss rates, memory usage, and runtime performance. We observed that the
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proposed allocator demonstrated significant improvements in reducing TLB misses,
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leading to noticeable enhancements in runtime efficiency for both micro and macro
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benchmarks. The behavior of specific allocation patterns and their impact on memory
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performance is detailed, providing a nuanced understanding of the allocator's effectiveness.
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</p>
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<p>
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Based on the evaluated results, the usability of the proposed allocator shows promise
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for applications requiring optimized memory management and reduced overhead from TLB misses.
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However, limitations were also identified, such as scenarios where the allocator's performance
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gains were marginal or where it introduced additional complexity in memory management. These
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limitations provide a roadmap for future optimizations and refinements of the allocator design.
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</p>
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</div>
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<div id="outline-container-org2f83090" class="outline-3">
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<h3 id="org2f83090"><span class="section-number-3">1.1.</span> Expirement setup</h3>
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<div class="outline-text-3" id="text-1-1">
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<p>
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The CHERI Morello board was used to evaluate the proposed memory allocator.
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Morello implements the ARM A76 with enhanced server-class memory, featuring a
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quad-core ARM CPU with capability extensions. The L1 and L2 caches were modified
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to proliferate the capability bit, ensuring compatibility with CHERI's capability-based
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memory model. When compiling the C programs for benchmarking, the Benchmark ABI was
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used as recommended by the CHERI community. This compilation mode was enabled using
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the Clang compiler.
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</p>
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<p>
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The Benchmark ABI was specifically designed because the Morello branch predictor
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was not expanded to predict bounds. Consequently, a capability-based jump introduces
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stalls in later PCC-dependent instructions until bounds are established. This issue
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is particularly significant during dynamically linked calls and returns between
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libraries, where bounds are changed to cover the called or returned-to library.
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Such stalls can negatively affect performance, making the Benchmark ABI an essential
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consideration for this evaluation.
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</p>
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<p>
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Each C program was executed using two different memory allocators. The first was
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the modified C allocator, imported as a header file. This approach was necessary
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because the Benchmark ABI shared object file exhibited unexpected behavior,
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failing to overwrite the C program at runtime with the intended malloc functions.
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The second allocator was the standard OS memory allocator, which, in the case of
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CHERIBSD, is Jemalloc.
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</p>
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<p>
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Performance measurements were carried out using ARM performance counters to
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ensure accurate evaluation. These counters provided detailed metrics, allowing
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us to compare the performance of the two allocators and assess the impact of
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the proposed changes.
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</p>
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</div>
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<div id="outline-container-org0d440d4" class="outline-4">
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<h4 id="org0d440d4"><span class="section-number-4">1.1.1.</span> Performance counters used</h4>
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<div class="outline-text-4" id="text-1-1-1">
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<!-- This HTML table template is generated by emacs 29.1 -->
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<table border="1">
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<tr>
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<td align="left" valign="top">
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Performance counter
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</td>
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<td align="left" valign="top">
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Description
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</td>
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</tr>
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<tr>
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<td align="left" valign="top">
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Wall clock <br />
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<br />
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<br />
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(p/l1d_tlb_rd) L1 data TLB reads <br />
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<br />
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(p/l2d_tlb_rd) L2 data TLB reads <br />
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<br />
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(p/l1d_tlb_refill) L1 data TLB refills <br />
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<br />
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<br />
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<br />
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<br />
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<br />
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<br />
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<br />
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<br />
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<br />
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(p/cpu_cycles) CPU cycles <br />
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<br />
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<br />
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<br />
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<br />
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<br />
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<br />
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(p/dtlb_walk) Data TLB walks <br />
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<br />
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<br />
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(p/ll_cache_miss_rd) Last level cache miss reads <br />
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<br />
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<br />
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</td>
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<td align="left" valign="top">
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The actual time taken from the start of a <br />
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computer program to the end. <br />
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<br />
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Level 1 data TLB access, read <br />
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<br />
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Level 2 data TLB access, read <br />
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<br />
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Level 1 data TLB refill. <br />
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The Level 1 data TLB refill <br />
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counter tracks each access to <br />
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the L1D_TLB that results <br />
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in a refill of the Level 1 data <br />
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or unified TLB. This includes any <br />
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access that requires a memory lookup <br />
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due to a translation table walk <br />
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or accessing another level of TLB cache. <br />
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<br />
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The CPU CYCLES counter increases with <br />
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every clock cycle. However, it can be <br />
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affected by changes in clock frequency, <br />
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such as when WFI (Wait for Interrupt) <br />
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or WFE (Wait for Event) <br />
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instructions pause the clock. <br />
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<br />
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Data TLB access with at least <br />
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one translation table walk. <br />
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<br />
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Last level cache miss, read <br />
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(This refers to every miss in the <br />
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Last level cache that occurs <br />
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during a memory read operation.)
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</td>
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</tr>
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</table>
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</div>
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</div>
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<div id="outline-container-org9cacc1c" class="outline-4">
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<h4 id="org9cacc1c"><span class="section-number-4">1.1.2.</span> Benchmarks</h4>
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<div class="outline-text-4" id="text-1-1-2">
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<p>
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The benchmarks are classified into 2 classes:
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</p>
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</div>
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<ol class="org-ol">
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<li><a id="orge18d7e4"></a>Micro benchmark<br />
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<div class="outline-text-5" id="text-1-1-2-1">
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<ul class="org-ul">
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<li>GLIBC: The Glibc benchmark evaluates the performance of
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malloc and free functions in single-threaded, multi-threaded,
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and emulated multi-threading scenarios using various block sizes and
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allocation patterns. It simulates real-world memory usage by partially
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deallocating blocks in FIFO order and fully deallocating them in LIFO order.
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Results are gathered across configurations to analyze performance variations.</li>
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<li>MemAccess: This benchmark by Alex Bordei evaluates the performance impact of
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memory access patterns by constructing and traversing a doubly
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linked list with varying working set sizes. It supports sequential or
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randomized structures, optional node operations, and multithreaded
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traversal using pthreads. The program dynamically allocates memory and systematically
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doubles the working set size to analyze memory hierarchy behavior.</li>
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</ul>
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</div>
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</li>
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<li><a id="org697b307"></a>Macro runs<br />
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<div class="outline-text-5" id="text-1-1-2-2">
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<ul class="org-ul">
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<li>Kmeans: Kmeans implements a parallelized K-means clustering algorithm that
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assigns data points to clusters based on proximity to centroids,
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iteratively updating them until convergence. The computation is
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|
distributed across threads using the pthread library, dynamically
|
|
assigning tasks to optimize performance. Parameters like data size
|
|
and clusters are configurable, and the program ensures efficient
|
|
memory management and synchronization.</li>
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|
<li>Richards: Richards is a task scheduling benchmark that simulates a
|
|
multitasking environment with tasks of varying types and priorities,
|
|
communicating through queued packets. The schedule function manages
|
|
task execution based on state and priority, tracking processed packets
|
|
and held tasks for performance evaluation. Configurable iterations and
|
|
timing help measure system performance and ensure correctness.</li>
|
|
</ul>
|
|
</div>
|
|
</li>
|
|
</ol>
|
|
</div>
|
|
</div>
|
|
|
|
<div id="outline-container-orgcc0820e" class="outline-3">
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<h3 id="orgcc0820e"><span class="section-number-3">1.2.</span> Results</h3>
|
|
<div class="outline-text-3" id="text-1-2">
|
|
|
|
<div id="org0a8604a" class="figure">
|
|
<p><img src="./diagrams/allbenchmarks.png" alt="allbenchmarks.png" align="right" />
|
|
</p>
|
|
</div>
|
|
|
|
|
|
<div id="org7ada87f" class="figure">
|
|
<p><img src="./diagrams/kmeans.png" alt="kmeans.png" align="right" />
|
|
</p>
|
|
</div>
|
|
|
|
|
|
<div id="orgedd36f2" class="figure">
|
|
<p><img src="./diagrams/glibc.png" alt="glibc.png" align="right" />
|
|
</p>
|
|
</div>
|
|
</div>
|
|
</div>
|
|
|
|
<div id="outline-container-org1d8ebaa" class="outline-3">
|
|
<h3 id="org1d8ebaa"><span class="section-number-3">1.3.</span> Usability</h3>
|
|
</div>
|
|
</div>
|
|
</div>
|
|
<div id="postamble" class="status">
|
|
<p class="author">Author: Akilan</p>
|
|
<p class="date">Created: 2025-01-12 Sun 17:26</p>
|
|
<p class="validation"><a href="https://validator.w3.org/check?uri=referer">Validate</a></p>
|
|
</div>
|
|
</body>
|
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</html> |