52 lines
2.0 KiB
Plaintext
52 lines
2.0 KiB
Plaintext
; SPDX-License-Identifier: BSD-3-Clause
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; Copyright(c) 2010-2018 Intel Corporation
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; The pipeline below implements a simple pass-through connection between the
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; input ports to the output ports, as in this diagram:
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; ________________
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; LINK0 RXQ0 --->|................|---> LINK1 TXQ0
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; | |
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; LINK1 RXQ0 --->|................|---> LINK0 TXQ0
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; | PIPELINE0 |
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; LINK2 RXQ0 --->|................|---> LINK3 TXQ0
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; | |
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; LINK3 RXQ0 --->|................|---> LINK2 TXQ0
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; |________________|
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;
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mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
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link LINK0 dev 0000:02:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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link LINK1 dev 0000:02:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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link LINK2 dev 0000:06:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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link LINK3 dev 0000:06:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
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pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0
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pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0
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pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0
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pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0
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pipeline PIPELINE0 port out bsz 32 link LINK1 txq 0
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pipeline PIPELINE0 port out bsz 32 link LINK2 txq 0
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pipeline PIPELINE0 port out bsz 32 link LINK3 txq 0
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pipeline PIPELINE0 table match stub
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pipeline PIPELINE0 table match stub
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pipeline PIPELINE0 table match stub
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pipeline PIPELINE0 table match stub
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pipeline PIPELINE0 port in 0 table 0
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pipeline PIPELINE0 port in 1 table 1
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pipeline PIPELINE0 port in 2 table 2
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pipeline PIPELINE0 port in 3 table 3
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thread 1 pipeline PIPELINE0 enable
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pipeline PIPELINE0 table 0 rule add match default action fwd port 1
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pipeline PIPELINE0 table 1 rule add match default action fwd port 0
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pipeline PIPELINE0 table 2 rule add match default action fwd port 3
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pipeline PIPELINE0 table 3 rule add match default action fwd port 2
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