[C AtomicMem] INFO: try to allocate 2097152B
[C AtomicMem] INFO: allocate 2097152B mem
                  20 File L1PRqMshR   L1PRqMshrSafe top.memSys_dc_0_m_banks_0_pRqMshr: init empty entry done
                  40 L1CRqMshrSafe top.memSys_dc_0_m_banks_0_cRqMshr: init empty entry done
                 160 LLCRqMshrSafe top.memSys_llc_0.m_cRqMshr: init empty entry done
                6430 top Start Issuing Requests only now!!!!
                6440 L1 top cRqTransfer_new: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False  >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } }
                6450 L1 top.memSys_dc_0_m_banks_0_pipeline tagMatch: tagged CRq L1PipeRqIn { addr: 'h00000000001c0030, mshrIdx: 'h0 } ; 'h00000000000e0<V 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000  > ; <V I I I I  > ; <V tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid   > ; 
                6460 L1 top pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, repInfo: <V 'h0 'h1 'h2 'h3  > }
                6460 L1 top pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False  >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } }
                6460 L1 top pipelineResp: cRq: no owner, miss no replace
                6480 L1 top sendRqToP: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False  >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, id: 'h0, child:  }
                6510 XBar top.memSys_cRqXBar: deq src           0
                6510 XBAR top.memSys_cRqXBar: enq dst           0 ; CRqMsg { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, id: 'h0, child: 'h0 }
                6550 LL top.memSys_llc_0 cRqTransfer_new_child: 'h0 ; CRqMsg { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, id: 'h0, child: 'h0 } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V                                                                  >, id: tagged Child 'h0 }
                6560 LL top.memSys_llc_0.m_pipeline tagMatch: tagged CRq LLPipeCRqIn { addr: 'h00000000001c0030, mshrIdx: 'h0 } ; 'h0000000000038 ; <V 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000  > ; <V I I I I I I I I I I I I I I I I  > ; <V tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid   >
                6570 LL top.memSys_llc_0 pipelineResp: PipeOut { cmd: tagged LLCRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: <V I  >, owner: tagged Invalid , other:  }, line: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, repInfo:  }
                6570 LL top.memSys_llc_0 pipelineResp: cRq: 'h0 ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True  >, id: tagged Child 'h0 }
                6570 LL top.memSys_llc_0 pipelineResp: cRq: no owner, miss no replace: <V tagged Invalid   >
                6580 LL top.memSys_llc_0 sendToM: ToMemInfo { mshrIdx: 'h0, t: Ld } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True  >, id: tagged Child 'h0 } ; LLCRqSlot { way: 'h0, repTag: 'h0aaaaaaaaaaaa, waitP: True, dirPend: <V tagged Invalid   > } ; tagged Invalid  ; False
                6580 LL top.memSys_llc_0 sendToM: load only: tagged Ld LdMemRq { addr: 'h00000000001c0030, child: , id: LdMemRqId { refill: True, mshrIdx: 'h0 } }
                6920 LL top.memSys_llc_0 mRsTransfer: MemRsMsg { data: <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000  >, child: , id: LdMemRqId { refill: True, mshrIdx: 'h0 } } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True  >, id: tagged Child 'h0 } ; LLCRqSlot { way: 'h0, repTag: 'h0aaaaaaaaaaaa, waitP: True, dirPend: <V tagged Invalid   > } ; 
                6930 LL top.memSys_llc_0.m_pipeline tagMatch: tagged MRs LLPipeMRsCmd { addr: 'h00000000001c0030, way: 'h0 } ; 'h0000000000038 ; <V 'h0000000000038 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000  > ; <V I I I I I I I I I I I I I I I I  > ; <V tagged Valid CRqOwner { mshrIdx: 'h0, replacing: False } tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid   >
                6940 LL top.memSys_llc_0 pipelineResp: mRs: CRqOwner { mshrIdx: 'h0, replacing: False } ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True  >, id: tagged Child 'h0 } ; LLCRqSlot { way: 'h0, repTag: 'h0aaaaaaaaaaaa, waitP: True, dirPend: <V tagged Invalid   > }
                6940 LL top.memSys_llc_0 pipelineResp: cRq from child Hit func: 'h0 ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True  >, id: tagged Child 'h0 }
                6950 LL top.memSys_llc_0 sendRsToC: 'h0 ; LLRq { addr: 'h00000000001c0030, fromState: I, toState: S, canUpToE: True, child: 'h0, byteEn: <V False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True False True  >, id: tagged Child 'h0 } ; tagged Valid <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000  > ; E
                6980 XBar top.memSys_pXBar: deq src           0
                6980 XBAR top.memSys_pXBar: enq dst           0 ; tagged PRs PRsMsg { addr: 'h00000000001c0030, toState: E, child: , data: tagged Valid <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000  >, id: 'h0 }
                7020 L1 top pRsTransfer: PRsMsg { addr: 'h00000000001c0030, toState: E, child: , data: tagged Valid <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000  >, id: 'h0 }
                7030 L1 top.memSys_dc_0_m_banks_0_pipeline tagMatch: tagged PRs L1PipePRsCmd { addr: 'h00000000001c0030, way: 'h0 } ; 'h00000000000e0<V 'h00000000000e0 'h0000000000000 'h0000000000000 'h0000000000000  > ; <V I I I I  > ; <V tagged Valid 'h0 tagged Invalid  tagged Invalid  tagged Invalid   > ; 
                7040 L1 top pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h00000000000e0, cs: E, dir: , owner: tagged Valid 'h0, other:  }, line: <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000  > }, repInfo: <V 'h0 'h1 'h2 'h3  > }
                7040 L1 top pipelineResp: pRs: 
                7040 L1 top pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00000000, addr: 'h00000000001c0030, toState: S, op: Ld, byteEn: <V True True False True False False True False  >, data: 'h5c927455615b0017, amoInst: AmoInst { func: Min, doubleWord: True, aq: False, rl: False } }
                7040 L1 top pipelineResp: Hit func: update ram: <V 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000 'h00000000001c0000  > ; tagged Invalid 
start DMA request
                7070 LL top.memSys_llc_0 cRqTransfer_new_dma: 'h1 ; DmaRq { addr: 'h0000000000000000, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False  >, data: <V 'h59ad4f8c1a6389b5 'h7262438d537b614b 'h5089ba923e931c67 'h7aee26f5412250a9 'h0479e6ca06bedde8 'h2f0376f316d654e0 'h17e0fbfa5932e0e4 'h2fdb7c5f0c93dbbd  >, id: 'h00000000 } ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False  >, id: tagged Dma 'h00000000 }
                7080 LL top.memSys_llc_0.m_pipeline tagMatch: tagged CRq LLPipeCRqIn { addr: 'h0000000000000000, mshrIdx: 'h1 } ; 'h0000000000000 ; <V 'h0000000000038 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000 'h0000000000000  > ; <V E I I I I I I I I I I I I I I I  > ; <V tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid  tagged Invalid   >
                7090 LL top.memSys_llc_0 pipelineResp: PipeOut { cmd: tagged LLCRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: <V I  >, owner: tagged Invalid , other:  }, line: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, repInfo:  }
                7090 LL top.memSys_llc_0 pipelineResp: cRq: 'h1 ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False  >, id: tagged Dma 'h00000000 }
                7090 LL top.memSys_llc_0 pipelineResp: cRq from dma: no owner, miss req mem
                7100 LL top.memSys_llc_0 sendToM: ToMemInfo { mshrIdx: 'h1, t: DmaWr } ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False  >, id: tagged Dma 'h00000000 } ; LLCRqSlot { way: 'h1, repTag: 'h0aaaaaaaaaaaa, waitP: False, dirPend: <V tagged Invalid   > } ; tagged Valid <V 'h59ad4f8c1a6389b5 'h7262438d537b614b 'h5089ba923e931c67 'h7aee26f5412250a9 'h0479e6ca06bedde8 'h2f0376f316d654e0 'h17e0fbfa5932e0e4 'h2fdb7c5f0c93dbbd  > ; False
                7100 LL top.memSys_llc_0 sendToM: dma write: tagged Wb WbMemRs { addr: 'h0000000000000000, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False  >, data: <V 'h59ad4f8c1a6389b5 'h7262438d537b614b 'h5089ba923e931c67 'h7aee26f5412250a9 'h0479e6ca06bedde8 'h2f0376f316d654e0 'h17e0fbfa5932e0e4 'h2fdb7c5f0c93dbbd  > }
                7120 LL top.memSys_llc_0 sendRsToDma: St: 'h1 ; LLRq { addr: 'h0000000000000000, fromState: I, toState: M, canUpToE: False, child: 'h0, byteEn: <V True True False False True False True False True True True False True False True True False False False True False True False True True True False True True False True False True False False False False True False True True True True False True False True True False False True True False True True True False True False True True False False False  >, id: tagged Dma 'h00000000 }
