From 001c5e8347b38807dbecbea02e6317b1d1fbf363 Mon Sep 17 00:00:00 2001
From: Franz Fuchs <franz.fuchs@cl.cam.ac.uk>
Date: Fri, 5 Nov 2021 13:47:39 +0000
Subject: [PATCH] put changing the interrupt counter and writing back to a
 register in the right order

---
 src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index eb53a5a..168b20b 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -710,10 +710,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
 `ifdef PERFORMANCE_MONITORING
         EventsCore events = unpack(0);
         events.evt_TRAP = 1;
-        events_reg <= events;
         if(trap matches tagged Interrupt .i) begin
             events.evt_INTERRUPT = 1;
         end
+        events_reg <= events;
 `endif
         // checks
         doAssert(x.rob_inst_state == Executed, "must be executed");