diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv
index 31f51ee..0fc4a62 100644
--- a/src_Core/CPU/CsrFile.bsv
+++ b/src_Core/CPU/CsrFile.bsv
@@ -1122,7 +1122,8 @@ module mkCsrFile #(Data hartid)(CsrFile);
                     excInstAccessFault, excInstPageFault,
                     excLoadAddrMisaligned, excLoadAccessFault,
                     excStoreAddrMisaligned, excStoreAccessFault,
-                    excLoadPageFault, excStorePageFault, excStoreCapPageFault: return addr;
+                    excLoadPageFault, excStorePageFault,
+                    excStoreCapPageFault, excLoadCapPageFault: return addr;
 
                     default: return 0;
                 endcase);
diff --git a/src_Core/RISCY_OOO/procs/lib/TlbTypes.bsv b/src_Core/RISCY_OOO/procs/lib/TlbTypes.bsv
index 9cae2f9..5d83297 100644
--- a/src_Core/RISCY_OOO/procs/lib/TlbTypes.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/TlbTypes.bsv
@@ -243,6 +243,7 @@ function TlbPermissionCheck hasVMPermission(
                 fault = True;
             end
             if (cap) begin
+                if (!fault) excCode = excLoadCapPageFault;
                 // check for invalid PTE encodings
                 if ((!pte_upper_type.cap_readable && pte_upper_type.cap_read_gen) ||
                     (pte_upper_type.cap_readable && !pte_upper_type.cap_read_mod &&