diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 3e91399..1c16a97 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -1319,7 +1319,7 @@ module mkCore#(CoreId coreId)(Core);
       l2Tlb.updateVMInfo(vmI, vmD);
 
       let startpc = csrf.dpc_read;
-      fetchStage.redirect (PredState{pc: cast(startpc)});
+      fetchStage.redirect (cast(startpc));
       renameStage.debug_resume;
       commitStage.debug_resume;
 
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
index e40eb1a..f7b529e 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
@@ -747,7 +747,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
                                        ? 4
                                        : 1));
              csrf.dcsr_cause_write (dcsr_cause);
-             csrf.dpc_write (cast(trap.ps.pc));
+             csrf.dpc_write (cast(trap.pc));
 
              // Tell fetch stage to wait for redirect
              // Note: rule doCommitTrap_flush may have done this already; redundant call is ok.