From 02ba37bf6ad4e08591f542f7fe3ec861f19a7b51 Mon Sep 17 00:00:00 2001 From: Alexandre Joannou Date: Thu, 8 Sep 2022 13:20:35 +0000 Subject: [PATCH] Report the actual running state to the debug module --- src_Core/CPU/Core.bsv | 2 ++ src_Core/CPU/Proc.bsv | 3 +++ src_Core/CPU/Proc_IFC.bsv | 1 + src_Core/Core/CoreW.bsv | 16 +++++++++------- src_Core/Debug_Module/DM_Run_Control.bsv | 10 ++++++---- src_Core/Debug_Module/Debug_Module.bsv | 2 ++ 6 files changed, 23 insertions(+), 11 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 5a03609..1dcca4a 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -196,6 +196,7 @@ interface Core; `ifdef INCLUDE_GDB_CONTROL interface Server #(Bool, Bool) hart_run_halt_server; interface Server #(DM_CPU_Req #(5, 64), DM_CPU_Rsp #(64)) hart_gpr_mem_server; + interface Get #(Bool) core_is_running; `ifdef ISA_F interface Server #(DM_CPU_Req #(5, 64), DM_CPU_Rsp #(64)) hart_fpr_mem_server; `endif @@ -1589,6 +1590,7 @@ module mkCore#(CoreId coreId)(Core); `ifdef INCLUDE_GDB_CONTROL interface Server hart_run_halt_server = toGPServer (f_run_halt_reqs, f_run_halt_rsps); interface Server hart_gpr_mem_server = toGPServer (f_gpr_reqs, f_gpr_rsps); + interface core_is_running = toGet (rg_core_run_state == CORE_RUNNING); `ifdef ISA_F interface Server hart_fpr_mem_server = toGPServer (f_fpr_reqs, f_fpr_rsps); `endif diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 31bc72e..b8b00d7 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -263,6 +263,7 @@ module mkProc (Proc_IFC); endinterface; function proj_run_halt_server (x) = x.hart_run_halt_server; function proj_gpr_mem_server (x) = x.hart_gpr_mem_server; + function proj_core_is_running (x) = x.core_is_running; `ifdef ISA_F function proj_fpr_mem_server (x) = x.hart_fpr_mem_server; `endif @@ -346,6 +347,8 @@ module mkProc (Proc_IFC); interface harts_put_other_req = replicate(emptyPut); interface harts_gpr_mem_server = map(proj_gpr_mem_server, core); + + interface harts_is_running = map (proj_core_is_running, core); `ifdef ISA_F interface harts_fpr_mem_server = map(proj_fpr_mem_server, core); `endif diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index abadfba..50c6e09 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -120,6 +120,7 @@ interface Proc_IFC; `ifdef INCLUDE_GDB_CONTROL interface Vector #(CoreNum, Server #(Bool, Bool)) harts_run_halt_server; interface Vector #(CoreNum, Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN))) harts_gpr_mem_server; + interface Vector #(CoreNum, Get #(Bool)) harts_is_running; `ifdef ISA_F interface Vector #(CoreNum, Server #(DM_CPU_Req #(5, FLEN), DM_CPU_Rsp #(FLEN))) harts_fpr_mem_server; `endif diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index cd432b5..b4ca732 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -270,7 +270,6 @@ module mkCoreW_reset #(Reset porReset) // ================================================================ // Start the proc a suitable time after a PoR - Bool start_running = False; UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait, reset_by porReset); rule rl_step_0 (rg_corew_start_after_por != 0); @@ -278,7 +277,7 @@ module mkCoreW_reset #(Reset porReset) rg_corew_start_after_por <= n; if (n==0) begin $display ("%0d: %m.rl_step_0, n = 0, do_release", cur_cycle); - do_release(start_running, rg_tohost_addr); + do_release (True, rg_tohost_addr); end endrule @@ -286,14 +285,16 @@ module mkCoreW_reset #(Reset porReset) // Hart-reset from DM `ifdef INCLUDE_GDB_CONTROL - Reg #(Bit #(8)) rg_harts_reset_delay <- mkReg (0); - Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0); + Reg #(Bool) rg_harts_reset_running <- mkReg (False); + Reg #(Bit #(8)) rg_harts_reset_delay <- mkReg (0); + Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0); for (Integer core = 0; core < valueOf(CoreNum); core = core + 1) rule rl_dm_harts_reset (rg_harts_reset_delay == 0); let x <- debug_module.harts_reset_client[core].request.get; dm_harts_reset_controller[core].assertReset; rg_harts_reset_delay <= fromInteger (hart_reset_duration + 200); // NOTE: heuristic + rg_harts_reset_running <= x; $display ("%0d: %m.rl_dm_harts_reset: asserting harts reset for %0d cycles", cur_cycle, hart_reset_duration); endrule @@ -301,10 +302,10 @@ module mkCoreW_reset #(Reset porReset) rule rl_dm_harts_reset_wait (rg_harts_reset_delay != 0); if (rg_harts_reset_delay == 1) begin let pc = soc_map_struct.pc_reset_value; - proc.start (start_running, pc, rg_tohost_addr, rg_fromhost_addr); + proc.start (rg_harts_reset_running, pc, rg_tohost_addr, rg_fromhost_addr); // We reset all the harts, so we indicate this to the DM, even though it's possible only one hart was requested to reset for (Integer core = 0; core < valueOf(CoreNum); core = core + 1) - debug_module.harts_reset_client[core].response.put (start_running); + debug_module.harts_reset_client[core].response.put (?); $display ("%0d: %m.rl_dm_harts_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h", cur_cycle, pc, rg_tohost_addr, rg_fromhost_addr); end @@ -319,6 +320,7 @@ module mkCoreW_reset #(Reset porReset) mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server, reset_by porReset); mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req, reset_by porReset); + mkConnection (debug_module.harts_is_running, proc.harts_is_running, reset_by porReset); `endif `ifdef INCLUDE_TANDEM_VERIF @@ -526,7 +528,7 @@ module mkCoreW_reset #(Reset porReset) ndm_reset_delay <= ndm_reset_delay - 1; endrule rule rl_debug_module_ack_reset (ndm_reset_delay == 1); - debug_module.ndm_reset_client.response.put (ndm_reset_restart_running); + debug_module.ndm_reset_client.response.put (?); do_release (ndm_reset_restart_running, rg_tohost_addr); ndm_reset_delay <= 0; endrule diff --git a/src_Core/Debug_Module/DM_Run_Control.bsv b/src_Core/Debug_Module/DM_Run_Control.bsv index 92d3ce0..c8ac9c9 100644 --- a/src_Core/Debug_Module/DM_Run_Control.bsv +++ b/src_Core/Debug_Module/DM_Run_Control.bsv @@ -60,6 +60,7 @@ interface DM_Run_Control_IFC; interface Vector #(CoreNum, Client #(Bool, Bool)) harts_reset_client; interface Vector #(CoreNum, Client #(Bool, Bool)) harts_client_run_halt; interface Vector #(CoreNum, Get #(Bit #(4))) harts_get_other_req; + interface Vector #(CoreNum, Put #(Bool)) harts_is_running; // ---------------- // Facing Platform: Non-Debug-Module Reset (reset all except DM) @@ -323,7 +324,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); rule rl_harts_reset_rsp; Bool running <- pop (f_harts_reset_rsps[core]); rg_harts_hasreset[core] <= False; - rg_harts_running[core] <= running; + //rg_harts_running[core] <= running; if (verbosity != 0) $display ("%0d: %m.rl_harts_reset_rsp: hart %0d running = ", cur_cycle, core, fshow (running)); @@ -332,7 +333,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); // Response from system for NDM reset rule rl_ndm_reset_rsp; Bool running <- pop (f_ndm_reset_rsps); - writeVReg(rg_harts_running, replicate(running)); + //writeVReg(rg_harts_running, replicate(running)); rg_ndm_reset_pending <= False; if (verbosity != 0) @@ -343,7 +344,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); // Response from system for run/halt request rule rl_harts_run_rsp (! f_ndm_reset_rsps.notEmpty); let running <- pop (f_harts_run_halt_rsps[core]); - rg_harts_running[core] <= running; + //rg_harts_running[core] <= running; if (running) rg_harts_resumeack[core] <= True; @@ -367,7 +368,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); mapM_(proj_clear, f_harts_reset_reqs); mapM_(proj_clear, f_harts_reset_rsps); - writeVReg(rg_harts_running, replicate(True)); // Safe approximation of whether the CPU is running or not + //writeVReg(rg_harts_running, replicate(True)); // Safe approximation of whether the CPU is running or not mapM_(proj_clear, f_harts_run_halt_reqs); mapM_(proj_clear, f_harts_run_halt_rsps); @@ -427,6 +428,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC); interface harts_reset_client = zipWith(toGPClient, f_harts_reset_reqs, f_harts_reset_rsps); interface harts_client_run_halt = zipWith(toGPClient, f_harts_run_halt_reqs, f_harts_run_halt_rsps); interface harts_get_other_req = map (toGet, f_harts_other_reqs); + interface harts_is_running = map (toPut, rg_harts_running); // ---------------- // Facing Platform: Non-Debug-Module Reset (reset all except DM) diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 90f1981..d3546cb 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -116,6 +116,7 @@ interface Debug_Module_IFC; interface Vector #(CoreNum, Client #(Bool, Bool)) harts_reset_client; interface Vector #(CoreNum, Client #(Bool, Bool)) harts_client_run_halt; interface Vector #(CoreNum, Get #(Bit #(4))) harts_get_other_req; + interface Vector #(CoreNum, Put #(Bool)) harts_is_running; // GPR access interface Vector #(CoreNum, Client #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN))) harts_gpr_mem_client; @@ -311,6 +312,7 @@ module mkDebug_Module (Debug_Module_IFC); interface harts_reset_client = dm_run_control.harts_reset_client; interface harts_client_run_halt = dm_run_control.harts_client_run_halt; interface harts_get_other_req = dm_run_control.harts_get_other_req; + interface harts_is_running = dm_run_control.harts_is_running; // GPR access interface harts_gpr_mem_client = dm_abstract_commands.harts_gpr_mem_client;