diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv
index d7dfddd..113906e 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv
@@ -116,6 +116,7 @@
     // L1
     `define LOG_L1_LINES 6 // 2KB
     `define LOG_L1_WAYS 1 // 2 ways
+    `define L1D_CRQ_NUM 8 // 8 L1D MSHRs
 
     // LLC
     `define LOG_LLC_LINES 8 // 8KB
diff --git a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
index aab5e41..558fd5a 100644
--- a/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv
@@ -103,7 +103,11 @@ typedef Bit#(DIndexSz) DIndex;
 typedef GetTagSz#(LgDBankNum, LgDSetNum) DTagSz;
 typedef Bit#(DTagSz) DTag;
 
+`ifdef L1D_CRQ_NUM
+typedef `L1D_CRQ_NUM DCRqNum;
+`else
 typedef L1WayNum DCRqNum;
+`endif
 typedef 4 DPRqNum; // match cache pipeline latency
 typedef Bit#(TLog#(DCRqNum)) DCRqMshrIdx;
 typedef Bit#(TLog#(DPRqNum)) DPRqMshrIdx;