Bump BSV-RVFI-DII and refactor to support new parcel-based interface

This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.

src_Core/CPU/Core.bsv

@@ -270,10 +270,7 @@ module mkCore#(CoreId coreId)(Core);
     // bridge that can insert instructions.
 `ifdef RVFI_DII
     Toooba_RVFI_DII_Bridge_IFC rvfi_bridge <- mkTooobaRVFIDIIBridge;
-    mkConnection(rvfi_bridge.dii, fetchStage.dii);
-    rule rl_passLastId;
-        fetchStage.lastTraceId(rvfi_bridge.lastId);
-    endrule
+    mkConnection(rvfi_bridge.dii, fetchStage.diiIfc);
 `endif
 
     // back end
@@ -399,7 +396,7 @@ module mkCore#(CoreId coreId)(Core);
                     epochManager.incrementEpoch;
                     fetchStage.redirect(new_pc
 `ifdef RVFI_DII
-                    , inst_tag.diid + 1
+                    , inst_tag.dii_next_pid
 `endif
                     );
                     globalSpecUpdate.incorrectSpec(False, spec_tag, inst_tag);

src_Core/CPU/Proc_IFC.bsv

@@ -43,7 +43,7 @@ import Trace_Data2 :: *;
 `endif
 
 `ifdef RVFI_DII
-import Types :: *;
+import ProcTypes :: *;
 `endif
 
 `ifdef DEBUG_WEDGE