Cheri-research/Toooba
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Bump BSV-RVFI-DII and refactor to support new parcel-based interface

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This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
This commit is contained in:
Jessica Clarke
2020-07-21 13:24:39 +01:00
parent 7d98946103
commit 0516db5e8d
13 changed files with 247 additions and 184 deletions
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15
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -47,6 +47,7 @@ import CHERICap::*;
import CHERICC_Fat::*;
import ISA_Decls_CHERI::*;
`ifdef RVFI_DII
import GetPut::*;
import RVFI_DII_Types::*;
`endif
import ISA_Decls_CHERI::*;
@@ -80,10 +81,22 @@ typedef struct {
SingleScalarPtr ptr; // pointer within a way
InstTime t; // inst time in ROB (for dispatch in reservation station)
`ifdef RVFI_DII
Dii_Id diid;
Dii_Parcel_Id dii_next_pid;
`endif
} InstTag deriving(Bits, Eq, FShow);
`ifdef RVFI_DII
typedef Vector#(SupSize, Maybe#(RVFI_DII_Execution #(64, 64))) Rvfi_Traces;
typedef Vector#(TMul#(SupSize, 2), RVFI_DII_Parcel_Resp) Dii_Parcel_Resps;
typedef Vector#(TMul#(SupSize, 2), Bit#(16)) Dii_Parcels;
interface Toooba_RVFI_DII_Server;
interface Get#(Dii_Parcel_Id) seqReqFirst;
interface Put#(Dii_Parcel_Resps) parcelResps;
interface Get#(Rvfi_Traces) trace_report;
endinterface
`endif
typedef `SB_SIZE SBSize;
typedef Bit#(TLog#(SBSize)) SBIndex;

8
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
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@@ -112,7 +112,7 @@ typedef struct {
// speculation
SpecBits spec_bits;
`ifdef RVFI_DII
Dii_Id diid;
Dii_Parcel_Id dii_pid;
`endif
`ifdef RVFI
ExtraTraceBundle traceBundle;
@@ -277,7 +277,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
Reg#(Bool) epochIncremented <- mkRegU;
Ehr#(3, SpecBits) spec_bits <- mkEhr(?);
`ifdef RVFI_DII
Reg#(Dii_Id) diid <- mkRegU;
Reg#(Dii_Parcel_Id) dii_pid <- mkRegU;
`endif
`ifdef RVFI
Ehr#(TAdd#(2, TAdd#(fpuMulDivExeNum, aluExeNum)), ExtraTraceBundle) traceBundle <- mkEhr(?);
@@ -437,7 +437,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
lsqAtCommitNotified[lsqNotified_enq_port] <= False;
nonMMIOStDone[nonMMIOSt_enq_port] <= False;
`ifdef RVFI_DII
diid <= x.diid;
dii_pid <= x.dii_pid;
`endif
`ifdef RVFI
//$display("%t : traceBundle = ", $time(), fshow(x.traceBundle), " in write_enq for %x", pc);
@@ -476,7 +476,7 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
nonMMIOStDone: nonMMIOStDone[nonMMIOSt_deq_port],
epochIncremented: epochIncremented,
`ifdef RVFI_DII
diid: diid,
dii_pid: dii_pid,
`endif
`ifdef RVFI
traceBundle: case (ppc_vaddr_csrData[pvc_deq_port]) matches

17
src_Core/RISCY_OOO/procs/lib/Types.bsv
View File

@@ -177,20 +177,3 @@ function Action doAssert(Bool b, String s) = action if(!b) $fdisplay(stderr, "\n
`else
function Action doAssert(Bool b, String s) = dynamicAssert(b, s);
`endif
`ifdef RVFI_DII
typedef Vector#(`sizeSup, Maybe#(RVFI_DII_Execution #(64, 64))) Rvfi_Traces;
typedef Vector#(`sizeSup, Maybe#(Dii_Id)) Dii_Ids;
typedef Vector#(`sizeSup, Maybe#(Bit#(32))) Dii_Insts;
typedef struct {
Dii_Insts insts;
Dii_Ids ids;
} InstsAndIDs deriving(Bits, Eq, FShow);
interface Toooba_RVFI_DII_Server;
interface Get#(Dii_Ids) seqReq;
interface Put#(InstsAndIDs) inst;
interface Get#(Rvfi_Traces) trace_report;
endinterface
`endif