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Bump BSV-RVFI-DII and refactor to support new parcel-based interface

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This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
This commit is contained in:
Jessica Clarke
2020-07-21 13:24:39 +01:00
parent 7d98946103
commit 0516db5e8d
13 changed files with 247 additions and 184 deletions
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13
src_Testbench/Top/Top_HW_Side.bsv
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@@ -70,8 +70,9 @@ import Debug_Module :: *;
`endif
`ifdef RVFI_DII
import RVFI_DII :: *;
import Types :: *;
import RVFI_DII :: *;
import Types :: *;
import ProcTypes :: *;
`endif
// ================================================================
@@ -458,14 +459,14 @@ module mkTop_HW_Side(Empty)
rg_banner_printed <= True;
endrule
RVFI_DII_Bridge #(DataSz, DataSz, `sizeSup) bridge <- mkRVFI_DII_Bridge("", 5001);
RVFI_DII_Bridge #(DataSz, DataSz, TMul#(SupSize, 2), SupSize) bridge <- mkRVFI_DII_Bridge("", 5001);
let dut <- mkPre_Top_HW_Side(reset_by bridge.new_rst);
mkConnection(bridge.client.report, dut.trace_report);
rule rl_provide_instr;
Dii_Ids reqs <- dut.seqReq.get;
Dii_Insts insts <- bridge.client.getInst(reqs);
dut.inst.put(InstsAndIDs{insts: insts, ids: reqs});
Dii_Parcel_Id req <- dut.seqReqFirst.get;
Dii_Parcel_Resps resps <- bridge.client.getParcels(req);
dut.parcelResps.put(resps);
endrule
endmodule