manual performance enable for dtlb

This commit is contained in:
2026-04-09 12:50:48 +01:00
parent 9f8a7eb9d8
commit 056d4e0821

View File

@@ -52,12 +52,12 @@ import LatencyTimer::*;
import HasSpecBits::*; import HasSpecBits::*;
import Vector::*; import Vector::*;
import Ehr::*; import Ehr::*;
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*; import PerformanceMonitor::*;
import CCTypes::*; import CCTypes::*;
import BlueUtils::*; import BlueUtils::*;
import StatCounters::*; import StatCounters::*;
`endif // `endif
export DTlbReq(..); export DTlbReq(..);
export DTlbResp(..); export DTlbResp(..);
@@ -123,9 +123,9 @@ interface DTlb#(type instT);
// performance // performance
interface Perf#(L1TlbPerfType) perf; interface Perf#(L1TlbPerfType) perf;
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
method EventsL1D events; method EventsL1D events;
`endif // `endif
endinterface endinterface
typedef FullAssocTlb#(DTlbSize) DTlbArray; typedef FullAssocTlb#(DTlbSize) DTlbArray;
@@ -210,7 +210,7 @@ module mkDTlb#(
// perf counters // perf counters
LatencyTimer#(DTlbReqNum, 12) latTimer <- mkLatencyTimer; // max latency: 4K cycles LatencyTimer#(DTlbReqNum, 12) latTimer <- mkLatencyTimer; // max latency: 4K cycles
Fifo#(1, L1TlbPerfType) perfReqQ <- mkCFFifo; Fifo#(1, L1TlbPerfType) perfReqQ <- mkCFFifo;
`ifdef PERF_COUNT // `ifdef PERF_COUNT
Fifo#(1, PerfResp#(L1TlbPerfType)) perfRespQ <- mkCFFifo; Fifo#(1, PerfResp#(L1TlbPerfType)) perfRespQ <- mkCFFifo;
Reg#(Bool) doStats <- mkConfigReg(False); Reg#(Bool) doStats <- mkConfigReg(False);
Count#(Data) accessCnt <- mkCount(0); Count#(Data) accessCnt <- mkCount(0);
@@ -251,10 +251,10 @@ module mkDTlb#(
function Bool isMiss(DTlbWait x) = x != None; function Bool isMiss(DTlbWait x) = x != None;
when(all(isMiss, readVReg(pendWait)), allMissCycles.incr(1)); when(all(isMiss, readVReg(pendWait)), allMissCycles.incr(1));
endrule endrule
`endif // `endif
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
Array #(Reg #(EventsL1D)) perf_events <- mkDRegOR (3, unpack (0)); Array #(Reg #(EventsL1D)) perf_events <- mkDRegOR (3, unpack (0));
`endif // `endif
// do flush: start when all misses resolve // do flush: start when all misses resolve
Bool noMiss = all(\== (False) , readVReg(pendValid_noMiss)); Bool noMiss = all(\== (False) , readVReg(pendValid_noMiss));
@@ -265,11 +265,11 @@ module mkDTlb#(
flushRqToPQ.enq(?); flushRqToPQ.enq(?);
waitFlushP <= True; waitFlushP <= True;
if(verbose) $display("[DTLB] flush begin"); if(verbose) $display("[DTLB] flush begin");
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
EventsL1D ev = unpack(0); EventsL1D ev = unpack(0);
ev.evt_TLB_FLUSH = 1; ev.evt_TLB_FLUSH = 1;
perf_events[2] <= ev; perf_events[2] <= ev;
`endif // `endif
endrule endrule
rule doFinishFlush(needFlush && waitFlushP); rule doFinishFlush(needFlush && waitFlushP);
@@ -365,7 +365,7 @@ module mkDTlb#(
// perf: miss // perf: miss
let lat <- latTimer.done(idx); let lat <- latTimer.done(idx);
`ifdef PERF_COUNT // `ifdef PERF_COUNT
if(doStats) begin if(doStats) begin
if(isValid(respForOtherReq)) begin if(isValid(respForOtherReq)) begin
missPeerLat.incr(zeroExtend(lat)); missPeerLat.incr(zeroExtend(lat));
@@ -376,13 +376,13 @@ module mkDTlb#(
missParentCnt.incr(1); missParentCnt.incr(1);
end end
end end
`endif // `endif
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
EventsL1D ev = unpack(0); EventsL1D ev = unpack(0);
ev.evt_TLB_MISS_LAT = saturating_truncate(lat); ev.evt_TLB_MISS_LAT = saturating_truncate(lat);
ev.evt_TLB_MISS = 1; ev.evt_TLB_MISS = 1;
perf_events[0] <= ev; perf_events[0] <= ev;
`endif // `endif
// conflict with wrong spec // conflict with wrong spec
wrongSpec_doPRs_conflict.wset(?); wrongSpec_doPRs_conflict.wset(?);
endrule endrule
@@ -573,17 +573,17 @@ module mkDTlb#(
if(verbose) $display("DTLB %m req (bare): ", fshow(r)); if(verbose) $display("DTLB %m req (bare): ", fshow(r));
end end
`ifdef PERF_COUNT // `ifdef PERF_COUNT
// perf: access // perf: access
if(doStats) begin if(doStats) begin
accessCnt.incr(1); accessCnt.incr(1);
end end
`endif // `endif
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
EventsL1D ev = unpack(0); EventsL1D ev = unpack(0);
ev.evt_TLB = 1; ev.evt_TLB = 1;
perf_events[1] <= ev; perf_events[1] <= ev;
`endif // `endif
// conflict with wrong spec // conflict with wrong spec
wrongSpec_procReq_conflict.wset(?); wrongSpec_procReq_conflict.wset(?);
endmethod endmethod
@@ -640,11 +640,11 @@ module mkDTlb#(
interface Perf perf; interface Perf perf;
method Action setStatus(Bool stats); method Action setStatus(Bool stats);
`ifdef PERF_COUNT // `ifdef PERF_COUNT
doStats <= stats; doStats <= stats;
`else // `else
noAction; // noAction;
`endif // `endif
endmethod endmethod
method Action req(L1TlbPerfType r); method Action req(L1TlbPerfType r);
@@ -652,27 +652,27 @@ module mkDTlb#(
endmethod endmethod
method ActionValue#(PerfResp#(L1TlbPerfType)) resp; method ActionValue#(PerfResp#(L1TlbPerfType)) resp;
`ifdef PERF_COUNT // `ifdef PERF_COUNT
perfRespQ.deq; perfRespQ.deq;
return perfRespQ.first; return perfRespQ.first;
`else // `else
perfReqQ.deq; // perfReqQ.deq;
return PerfResp { // return PerfResp {
pType: perfReqQ.first, // pType: perfReqQ.first,
data: 0 // data: 0
}; // };
`endif // `endif
endmethod endmethod
method Bool respValid; method Bool respValid;
`ifdef PERF_COUNT // `ifdef PERF_COUNT
return perfRespQ.notEmpty; return perfRespQ.notEmpty;
`else // `else
return perfReqQ.notEmpty; // return perfReqQ.notEmpty;
`endif // `endif
endmethod endmethod
endinterface endinterface
`ifdef PERFORMANCE_MONITORING // `ifdef PERFORMANCE_MONITORING
method EventsL1D events = perf_events[0]; method EventsL1D events = perf_events[0];
`endif // `endif
endmodule endmodule