From 059f189bbaf7e00b42db2228115215acb178bd80 Mon Sep 17 00:00:00 2001
From: jon <>
Date: Wed, 17 Feb 2021 14:35:49 +0000
Subject: [PATCH] Attempt to add all current source files to componenet.xml.
---
src_SSITH_P3/xilinx_ip/component.xml | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml
index 30c22e6..a3e4f16 100644
--- a/src_SSITH_P3/xilinx_ip/component.xml
+++ b/src_SSITH_P3/xilinx_ip/component.xml
@@ -2621,11 +2621,6 @@
verilogSource
IMPORTED_FILE
-
- hdl/mkTrace_Data2_to_Trace_Data.v
- verilogSource
- IMPORTED_FILE
-
hdl/mkTourGHistReg.v
verilogSource
@@ -2953,11 +2948,31 @@
verilogSource
IMPORTED_FILE
+
+ hdl/mkCoreW_Synth.v
+ verilogSource
+ IMPORTED_FILE
+
hdl/mkCoreW.v
verilogSource
IMPORTED_FILE
+
+ hdl/mkPLIC_16_CoreNumX2_7.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ hdl/module_capChecksExec.v
+ verilogSource
+ IMPORTED_FILE
+
+
+ hdl/module_capChecksMem.v
+ verilogSource
+ IMPORTED_FILE
+
hdl/mkDCRqMshrWrapper.v
verilogSource