diff --git a/src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv b/src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv index e7d8cba..25838b1 100644 --- a/src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv +++ b/src_Core/RISCY_OOO/procs/lib/SplitLSQ.bsv @@ -952,17 +952,7 @@ module mkSplitLSQ(SplitLSQ); // make wrongSpec conflict with all others (but not correctSpec method and // findIssue) - RWire#(void) wrongSpec_hit_conflict <- mkRWire; - RWire#(void) wrongSpec_enqIss_conflict <- mkRWire; - RWire#(void) wrongSpec_enq_conflict <- mkRWire; - RWire#(void) wrongSpec_cacheEvict_conflict <- mkRWire; - RWire#(void) wrongSpec_update_conflict <- mkRWire; - RWire#(void) wrongSpec_issue_conflict <- mkRWire; - RWire#(void) wrongSpec_respLd_conflict <- mkRWire; - RWire#(void) wrongSpec_deqLd_conflict <- mkRWire; - RWire#(void) wrongSpec_deqSt_conflict <- mkRWire; - RWire#(void) wrongSpec_verify_conflict <- mkRWire; - RWire#(void) wrongSpec_wakeBySB_conflict <- mkRWire; + PulseWire wrongSpec_conflict <- mkPulseWire; // make wrongSpec more urgent than firstSt (resolve bsc error) Wire#(Bool) wrongSpec_urgent_firstSt <- mkDWire(True); Map#(Bit#(10),Bit#(6),Int#(3),2) ldKillMap <- mkMapLossy(minBound); @@ -1148,7 +1138,7 @@ module mkSplitLSQ(SplitLSQ); end endrule - rule enqIssueQ(issueLdInfo.wget matches tagged Valid .info); + rule enqIssueQ(issueLdInfo.wget matches tagged Valid .info &&& !wrongSpec_conflict); if(verbose) begin $display("[LSQ - enqIss] ", fshow(info)); end @@ -1190,8 +1180,6 @@ module mkSplitLSQ(SplitLSQ); spec_bits: ld_specBits_enqIss[info.tag] }); ld_inIssueQ_enqIss[info.tag] <= True; - // make conflict with incorrect spec - wrongSpec_enqIss_conflict.wset(?); endrule // Verify SQ entry one by one @@ -1214,7 +1202,8 @@ module mkSplitLSQ(SplitLSQ); // NOTE that when SQ is full and all verified, verifyP will point to a // valid and verified entry rule verifySt(st_valid_verify[st_verifyP_verify] && - !st_verified_verify[st_verifyP_verify]); + !st_verified_verify[st_verifyP_verify] && + !wrongSpec_conflict); StQTag verP = st_verifyP_verify; // check if the entry can be verified. We should not fire this rule if @@ -1264,9 +1253,6 @@ module mkSplitLSQ(SplitLSQ); joinActions(map(setVerified, idxVec)); if(verbose) $display("[LSQ - verifySt] st_verifyP %d", verP); - - // make conflict with incorrect spec - wrongSpec_verify_conflict.wset(?); endrule `ifdef BSIM @@ -1450,10 +1436,7 @@ module mkSplitLSQ(SplitLSQ); endcase); endmethod - method ActionValue#(LSQHitInfo) getHit(LdStQTag t); - // Conflict with wrong spec. This makes cache pipelineResp rule - // conflict with wrong spec, and can help avoid scheduling cycle. - wrongSpec_hit_conflict.wset(?); + method ActionValue#(LSQHitInfo) getHit(LdStQTag t) if (!wrongSpec_conflict); return (case(t) matches tagged Ld .tag: (LSQHitInfo { waitWPResp: ld_waitWPResp_hit[tag], @@ -1478,7 +1461,7 @@ module mkSplitLSQ(SplitLSQ); MemInst mem_inst, Maybe#(PhyDst) dst, SpecBits spec_bits, - Bit#(16) pc_hash) if(ld_can_enq_wire); + Bit#(16) pc_hash) if(ld_can_enq_wire && !wrongSpec_conflict); if(verbose) begin $display("[LSQ - enqLd] enqP %d; ", ld_enqP, "; ", fshow(inst_tag), @@ -1531,14 +1514,12 @@ module mkSplitLSQ(SplitLSQ); ld_olderSt_enq[ld_enqP] <= Invalid; ld_olderStVerified_enq[ld_enqP] <= False; end - // make conflict with incorrect spec - wrongSpec_enq_conflict.wset(?); endmethod method Action enqSt(InstTag inst_tag, MemInst mem_inst, Maybe#(PhyDst) dst, - SpecBits spec_bits) if(st_can_enq_wire); + SpecBits spec_bits) if(st_can_enq_wire && !wrongSpec_conflict); if(verbose) begin $display("[LSQ - enqSt] enqP %d; ", st_enqP, "; ", fshow(inst_tag), @@ -1567,8 +1548,6 @@ module mkSplitLSQ(SplitLSQ); st_verified_enq[st_enqP] <= False; st_specBits_enq[st_enqP] <= spec_bits; st_atCommit_enq[st_enqP] <= False; - // make conflict with incorrect spec - wrongSpec_enq_conflict.wset(?); endmethod method Action updateData(StQTag t, MemTaggedData d); @@ -1583,7 +1562,7 @@ module mkSplitLSQ(SplitLSQ); method ActionValue#(LSQUpdateAddrResult) updateAddr( LdStQTag lsqTag, Maybe#(Trap) fault, Bool allowCap, Addr pa, Bool mmio, ByteOrTagEn shift_be - ); + ) if (!wrongSpec_conflict); // index vec for vector functions Vector#(LdQSize, LdQTag) idxVec = genWith(fromInteger); @@ -1749,9 +1728,6 @@ module mkSplitLSQ(SplitLSQ); end end - // make conflict with incorrect spec - wrongSpec_update_conflict.wset(?); - // return waiting for wp resp bit: for deciding whether the updating Ld // can be issued return LSQUpdateAddrResult { @@ -1766,7 +1742,7 @@ module mkSplitLSQ(SplitLSQ); method ActionValue#(LSQIssueLdResult) issueLd(LdQTag tag, Addr pa, ByteOrTagEn shift_be, - SBSearchRes sbRes); + SBSearchRes sbRes) if (!wrongSpec_conflict); if(verbose) begin $display("[LSQ - issueLd] ", fshow(tag), "; ", fshow(pa), "; ", fshow(shift_be), "; ", fshow(sbRes)); @@ -2035,9 +2011,6 @@ module mkSplitLSQ(SplitLSQ); end `endif - // make conflict with incorrect spec - wrongSpec_issue_conflict.wset(?); - return issRes; endmethod @@ -2054,7 +2027,7 @@ module mkSplitLSQ(SplitLSQ); return issueLdQ.first.data; endmethod - method ActionValue#(LSQRespLdResult) respLd(LdQTag t, MemTaggedData alignedData); + method ActionValue#(LSQRespLdResult) respLd(LdQTag t, MemTaggedData alignedData) if (!wrongSpec_conflict); let res = LSQRespLdResult { wrongPath: False, dst: Invalid, @@ -2103,8 +2076,6 @@ module mkSplitLSQ(SplitLSQ); $display("[LSQ - respLd] ", fshow(t), "; ", fshow(alignedData), "; ", fshow(res)); end - // make conflict with incorrect spec - wrongSpec_respLd_conflict.wset(?); // return return res; endmethod @@ -2129,7 +2100,7 @@ module mkSplitLSQ(SplitLSQ); }; endmethod - method Action deqLd if(deqLdGuard); + method Action deqLd if(deqLdGuard && !wrongSpec_conflict); LdQTag deqP = ld_deqP_deqLd; if(verbose) $display("[LSQ - deqLd] deqP %d", deqP); @@ -2176,9 +2147,6 @@ module mkSplitLSQ(SplitLSQ); endfunction Vector#(LdQSize, LdQTag) idxVec = genWith(fromInteger); joinActions(map(setReady, idxVec)); - - // make conflict with incorrect spec - wrongSpec_deqLd_conflict.wset(?); endmethod method StQDeqEntry firstSt if(deqStGuard && wrongSpec_urgent_firstSt); @@ -2199,7 +2167,7 @@ module mkSplitLSQ(SplitLSQ); }; endmethod - method Action deqSt if(deqStGuard); + method Action deqSt if(deqStGuard && !wrongSpec_conflict); StQTag deqP = st_deqP; if(verbose) $display("[LSQ - deqSt] deqP %d", deqP); @@ -2247,15 +2215,12 @@ module mkSplitLSQ(SplitLSQ); endfunction Vector#(LdQSize, LdQTag) idxVec = genWith(fromInteger); joinActions(map(resetSt, idxVec)); - - // make conflict with incorrect spec - wrongSpec_deqSt_conflict.wset(?); endmethod interface lookupPAddr = replicate(lookupAPAddr); `ifdef TSO_MM - method Action cacheEvict(LineAddr lineAddr); + method Action cacheEvict(LineAddr lineAddr) if (!wrongSpec_conflict); if(verbose) $display("[LSQ - cacheEvict] ", fshow(lineAddr)); // kill a load if it satisfies the following conditions: // (1) valid @@ -2285,14 +2250,11 @@ module mkSplitLSQ(SplitLSQ); doAssert(!ld_isMMIO_evict[killTag], "cannot kill MMIO"); doAssert(ld_memFunc[killTag] == Ld, "can only kill Ld"); end - - // make conflict with incorrect spec - wrongSpec_cacheEvict_conflict.wset(?); endmethod `else - method Action wakeupLdStalledBySB(SBIndex sbIdx); + method Action wakeupLdStalledBySB(SBIndex sbIdx) if (!wrongSpec_conflict); if(verbose) begin $display("[LSQ - wakeupBySB] ", fshow(sbIdx)); end @@ -2307,8 +2269,6 @@ module mkSplitLSQ(SplitLSQ); endfunction Vector#(LdQSize, LdQTag) idxVec = genWith(fromInteger); joinActions(map(setReady, idxVec)); - // make conflict with incorrect spec - wrongSpec_wakeBySB_conflict.wset(?); endmethod `endif @@ -2453,17 +2413,7 @@ module mkSplitLSQ(SplitLSQ); end // make conflict with others - wrongSpec_hit_conflict.wset(?); - wrongSpec_enqIss_conflict.wset(?); - wrongSpec_enq_conflict.wset(?); - wrongSpec_update_conflict.wset(?); - wrongSpec_issue_conflict.wset(?); - wrongSpec_respLd_conflict.wset(?); - wrongSpec_deqLd_conflict.wset(?); - wrongSpec_deqSt_conflict.wset(?); - wrongSpec_verify_conflict.wset(?); - wrongSpec_cacheEvict_conflict.wset(?); - wrongSpec_wakeBySB_conflict.wset(?); + wrongSpec_conflict.send(); // more urgent than firstSt wrongSpec_urgent_firstSt <= True; endmethod