diff --git a/libs/BlueStuff b/libs/BlueStuff
index 4dec54b..b4c948d 160000
--- a/libs/BlueStuff
+++ b/libs/BlueStuff
@@ -1 +1 @@
-Subproject commit 4dec54bc42f1705ecd5066bc0d65cd64ab12e32e
+Subproject commit b4c948d4b4ed670128470b34e2bee184f4843ccc
diff --git a/libs/TagController b/libs/TagController
index f3ce441..d0fca21 160000
--- a/libs/TagController
+++ b/libs/TagController
@@ -1 +1 @@
-Subproject commit f3ce4415bfd7a49a1d45d312110b2484d4d1a5aa
+Subproject commit d0fca216babe2fcbab4cf63635d1e82384200d2c
diff --git a/src_Core/CPU/LLC_AXI4_Adapter.bsv b/src_Core/CPU/LLC_AXI4_Adapter.bsv
index e92c7c2..94a3a0c 100644
--- a/src_Core/CPU/LLC_AXI4_Adapter.bsv
+++ b/src_Core/CPU/LLC_AXI4_Adapter.bsv
@@ -73,9 +73,9 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
             Bits#(childT, childSz),
             FShow#(ToMemMsg#(idT, childT)),
             FShow#(MemRsMsg#(idT, childT)),
-            Add#(SizeOf#(Line), 0, TAdd#(512, 4)),
-            Add#(c__, TAdd#(1, TAdd#(idSz, childSz)), Wd_MId) // LLC_AXI_ID must fit into the external ID.
-           ); // assert Line sz = 512 + 4 tags
+            Add#(SizeOf#(Line), 0, TAdd#(512, 4)), // assert Line sz = 512 + 4 tags
+            Add#(a__, SizeOf#(LLC_AXI_ID#(idT, childT)), Wd_MId) // LLC_AXI_ID must fit into the external ID.
+           );
 
    // Verbosity: 0: quiet; 1: LLC transactions; 2: loop detail
    Integer verbosity = 2;
diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile
index 4df6e47..d86f5e4 100644
--- a/src_SSITH_P3/Makefile
+++ b/src_SSITH_P3/Makefile
@@ -27,7 +27,7 @@ BSC_COMPILATION_FLAGS += \
 	-D ISA_PRIV_M  -D ISA_PRIV_S  -D ISA_PRIV_U  \
 	-D SV39 \
 	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \
-	-D CheriBusBytes=8 \
+	-D CheriBusBytes=64 \
 	-D CheriMasterIDWidth=1 \
 	-D CheriTransactionIDWidth=6 \
 	-D PERFORMANCE_MONITORING \
@@ -36,7 +36,7 @@ BSC_COMPILATION_FLAGS += \
 	-D Near_Mem_Caches    \
 	-D FABRIC64    \
 	-D CAP128 \
-	-D MEM64 \
+	-D MEM512 \
 	-D RISCV \
 	-D NO_SPEC_TRAINING -D NO_SPEC_REDIRECT -D NO_SPEC_STRAIGHT_PATH -D SPEC_RSB_FIXUP -D NO_SPEC_RSB_PUSH -D NO_SPEC_STL \
 	-D TSO_MM \
diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv
index 7f5ff60..5934091 100644
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -71,10 +71,10 @@ interface P3_Core_IFC;
    // Core CPU interfaces
 
    // CPU IMem to Fabric master interface
-   interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
+   interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph,
                                 0, 0, 0, 0, 0)  master0;
 
-   interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
+   interface AXI4_Master_Sig#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph,
                                 0, 0, 0, 0, 0)  master1;
 
    // External interrupt sources
@@ -165,6 +165,16 @@ module mkP3_Core (P3_Core_IFC);
            , CoreW_IFC #(N_External_Interrupt_Sources)) both
      <- mkCoreW_reset (dm_power_on_reset, reset_by ndm_reset);
    match {.otherRst, .corew} = both;
+   // AXI4 Narrower Master in front of cached memory master
+   AXI4_Shim#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
+      manager_0_narrow <- mkAXI4ShimFF;
+   AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,4), 0, 0, 0, 0, 0)
+      manager_0_wide_a <- toWider_AXI4_Slave(manager_0_narrow.slave);
+   AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,2), 0, 0, 0, 0, 0)
+      manager_0_wide_b <- toWider_AXI4_Slave(manager_0_wide_a);
+   AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
+      manager_0_wide   <- toWider_AXI4_Slave(manager_0_wide_b);
+   mkConnection(corew.manager_0,manager_0_wide);
 
 `ifdef INCLUDE_GDB_CONTROL
 
@@ -256,7 +266,7 @@ module mkP3_Core (P3_Core_IFC);
 
    // ================================================================
    // INTERFACE
-   let master0_sig <- toAXI4_Master_Sig (corew.manager_0);
+   let master0_sig <- toAXI4_Master_Sig (manager_0_narrow.master);
    let master1_sig <- toAXI4_Master_Sig (corew.manager_1);
    // ----------------------------------------------------------------
    // Core CPU interfaces