From 0701dea9a937c14cea88010df1b531bc1c5d2e30 Mon Sep 17 00:00:00 2001
From: jon <>
Date: Thu, 1 Apr 2021 07:08:46 +0100
Subject: [PATCH] Preserve name for verilog so component.xml doesn't have to be
 fixed.

---
 src_Core/RISCY_OOO/procs/lib/Btb.bsv | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src_Core/RISCY_OOO/procs/lib/Btb.bsv b/src_Core/RISCY_OOO/procs/lib/Btb.bsv
index 11371e7..72965ae 100644
--- a/src_Core/RISCY_OOO/procs/lib/Btb.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Btb.bsv
@@ -85,13 +85,12 @@ typedef struct {
 } VnD#(type data) deriving(Bits, Eq, FShow);
 
 (* synthesize *)
-module mkBtbSmall(NextAddrPred#(16));
-    NextAddrPred#(16) btb <- mkBtb;
+module mkBtb(NextAddrPred#(16));
+    NextAddrPred#(16) btb <- mkBtbCore;
     return btb;
 endmodule
 
-//(* synthesize *)
-module mkBtb(NextAddrPred#(hashSz))
+module mkBtbCore(NextAddrPred#(hashSz))
     provisos (NumAlias#(tagSz, TSub#(TSub#(TSub#(AddrSz,SizeOf#(BtbBank)), SizeOf#(BtbIndex)), PcLsbsIgnore)),
         Add#(1, a__, TDiv#(tagSz, hashSz)),
     Add#(b__, tagSz, TMul#(TDiv#(tagSz, hashSz), hashSz)));