From 0784902e45af3fb9b267d000f6ca2b81f91bcea2 Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Fri, 2 Feb 2024 13:26:15 +0000 Subject: [PATCH] Tune the instruction fetch FIFO to the lower-latency ICache. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index d752a64..5d1c1a7 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -408,7 +408,7 @@ module mkFetchStage(FetchStage); // Pipeline Stage FIFOs Fifo#(1, Addr) translateAddress <- mkCFFifo; - Fifo#(3, Fetch1ToFetch2) fetch1toFetch2 <- mkCFFifo; // FIFO should match I$ latency + Fifo#(2, Fetch1ToFetch2) fetch1toFetch2 <- mkCFFifo; // FIFO should match I$ latency // These two fifos needs a capacity of 3 for full throughput if we fire only when we can enq on all channels. SupFifo#(SupSizeX2, 3, Fetch2ToDecode) f2d <- mkUGSupFifo; // Unguarded to prevent the static analyser from exploding. SupFifo#(SupSize, 3, FromFetchStage) out_fifo <- mkSupFifo;