From 078d39b9df5cce11728c32cf5614e43dfcd0426c Mon Sep 17 00:00:00 2001 From: jon Date: Tue, 2 Jun 2020 09:40:37 +0100 Subject: [PATCH] Enable write bursts in LLC AXI4 adapter. --- src_Core/CPU/LLC_AXI4_Adapter.bsv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src_Core/CPU/LLC_AXI4_Adapter.bsv b/src_Core/CPU/LLC_AXI4_Adapter.bsv index 98ba0ea..60ec66b 100644 --- a/src_Core/CPU/LLC_AXI4_Adapter.bsv +++ b/src_Core/CPU/LLC_AXI4_Adapter.bsv @@ -76,9 +76,9 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) AXI4_Size size = 8; let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_default_mid, araddr: addr, - arlen: 0, // burst len = arlen+1 - arsize: size, - arburst: fabric_default_burst, + arlen: 7, // burst len = arlen+1 + arsize: 8, + arburst: INCR, arlock: fabric_default_lock, arcache: fabric_default_arcache, arprot: fabric_default_prot, @@ -115,16 +115,16 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc) end Addr line_addr = { ld.addr [63:6], 6'h0 }; // Addr of containing cache line - Addr offset = zeroExtend ( { rg_rd_req_beat, 3'b_000 } ); // Addr offset of 64b word for this beat - fa_fabric_send_read_req (line_addr | offset); + //Addr offset = zeroExtend ( { rg_rd_req_beat, 3'b_000 } ); // Addr offset of 64b word for this beat + fa_fabric_send_read_req (line_addr); - if (rg_rd_req_beat == 0) + //if (rg_rd_req_beat == 0) f_pending_reads.enq (ld); - if (rg_rd_req_beat == 7) + //if (rg_rd_req_beat == 7) llc.toM.deq; - rg_rd_req_beat <= rg_rd_req_beat + 1; + //rg_rd_req_beat <= rg_rd_req_beat + 1; endrule rule rl_handle_read_rsps;