From 08231b7e5cb8c36a337bee375737596133b6bf0e Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Wed, 8 Sep 2021 10:11:25 -0500 Subject: [PATCH] Hopefully don't wedge on ifetch bus error. We think that we were wedging on IFetch bus error. It appears that we didn't make the last instruction fragment valid in the bus error case, and expect that this path was not previously exercised. This change returns 0s (to hopefully make the error less subtle) in exactly the right number of fragments. --- src_Core/CPU/MMIOPlatform.bsv | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index 3ee7fbd..6954d11 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -968,10 +968,8 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, // Access fault Vector #(SupSizeX2, Maybe #(Instruction16)) resp = replicate (Invalid); for(Integer i = 0; i < valueof (SupSizeX2); i = i+1) begin - if (fromInteger (i) < fetchingWay) - resp [i] = Valid (fetchedInsts [i]); - else if (fromInteger (i) == fetchingWay) - resp [i] = tagged Invalid; + if (fromInteger (i) <= fetchingWay) + resp [i] = Valid (unpack(pack(0))); end cores[reqCore].pRs.enq (tagged InstFetch resp); state <= SelectReq;