From 0970951184eab9692a1be5e1013101bd0f78a0dc Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Tue, 17 Aug 2021 16:39:20 +0100 Subject: [PATCH] Fix decoding of lr / sc with explicit bounds. When decoding {lr,sc}.{b,h,w,d,c,q}.{ddc,cap} the IType was not being set correctly. For sc we also need to set the destination register. --- src_Core/RISCY_OOO/procs/lib/Decode.bsv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv index e2302c1..c20349a 100755 --- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv @@ -1262,7 +1262,11 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); f7_cap_Loads: begin dInst.iType = Ld; MemInst mi = exp_bnds_mem_inst.Valid; - if (isValid(exp_bnds_mem_inst)) dInst.execFunc = tagged Mem mi; + if (isValid(exp_bnds_mem_inst)) begin + dInst.execFunc = tagged Mem mi; + if (mi.mem_func == Lr) + dInst.iType = Lr; + end else illegalInst = True; regs.dst = Valid(tagged Gpr rd); regs.src1 = Valid(tagged Gpr rs1); @@ -1272,7 +1276,13 @@ function DecodeResult decode(Instruction inst, Bool cap_mode); f7_cap_Stores: begin dInst.iType = St; MemInst mi = exp_bnds_mem_inst.Valid; - if (isValid(exp_bnds_mem_inst)) dInst.execFunc = tagged Mem mi; + if (isValid(exp_bnds_mem_inst)) begin + dInst.execFunc = tagged Mem mi; + if (mi.mem_func == Sc) begin + dInst.iType = Sc; + regs.dst = Valid(tagged Gpr rs2); + end + end else illegalInst = True; regs.src1 = Valid(tagged Gpr rs1); regs.src2 = Valid(tagged Gpr rs2);