From 0f04b9cbe19732c820a5589580eac3df9dacec5d Mon Sep 17 00:00:00 2001
From: rsnikhil <nikhil@acm.org>
Date: Wed, 8 Jan 2020 19:49:49 -0500
Subject: [PATCH] Tweaks to builds/Resources/Include_..._.mk

---
 builds/Resources/Include_Common.mk    | 2 +-
 builds/Resources/Include_bluesim.mk   | 4 ++--
 builds/Resources/Include_verilator.mk | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/builds/Resources/Include_Common.mk b/builds/Resources/Include_Common.mk
index d03270c..e692ce9 100644
--- a/builds/Resources/Include_Common.mk
+++ b/builds/Resources/Include_Common.mk
@@ -38,7 +38,7 @@ CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/Core:$(RE
 
 TESTBENCH_DIRS  = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC:$(REPO)/src_Testbench/Fabrics/AXI4
 
-BSC_PATH = -p $(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):+
+BSC_PATH = $(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):+
 
 # ----------------
 # Top-level file and module
diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk
index 8186540..68e22d3 100644
--- a/builds/Resources/Include_bluesim.mk
+++ b/builds/Resources/Include_bluesim.mk
@@ -15,7 +15,7 @@ build_dir:
 .PHONY: compile
 compile: build_dir
 	@echo "INFO: Re-compiling Core (CPU, Caches)"
-	bsc -u -elab -sim  $(TMP_DIRS)  $(BSC_COMPILATION_FLAGS)  $(BSC_PATH)  $(TOPFILE)
+	bsc -u -elab -sim  $(TMP_DIRS)  $(BSC_COMPILATION_FLAGS)  -p $(BSC_PATH)  $(TOPFILE)
 	@echo "INFO: Re-compiled  Core (CPU, Caches)"
 
 # ================================================================
@@ -31,7 +31,7 @@ BSC_C_FLAGS += \
 .PHONY: simulator
 simulator:
 	@echo "INFO: linking bsc-compiled objects into Bluesim executable"
-	bsc -sim -parallel-sim-link 8 +RTS -K32M -RTS \
+	bsc -sim -parallel-sim-link 8 +RTS -K128M -RTS \
 		$(TMP_DIRS) \
 		-e $(TOPMODULE) -o ./$(SIM_EXE_FILE) \
 		$(BSC_C_FLAGS) \
diff --git a/builds/Resources/Include_verilator.mk b/builds/Resources/Include_verilator.mk
index 7779335..da2b943 100644
--- a/builds/Resources/Include_verilator.mk
+++ b/builds/Resources/Include_verilator.mk
@@ -18,7 +18,7 @@ Verilog_RTL:
 .PHONY: compile
 compile:  build_dir  Verilog_RTL
 	@echo  "INFO: Verilog RTL generation ..."
-	bsc -u -elab -verilog  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS)  $(BSC_PATH)  $(TOPFILE)
+	bsc -u -elab -verilog  $(RTL_GEN_DIRS)  $(BSC_COMPILATION_FLAGS)  -p $(BSC_PATH)  $(TOPFILE)
 	@echo  "INFO: Verilog RTL generation finished"
 
 # ================================================================