From 0f4e3f7c72cd1c289d04aabc6756966a9f399547 Mon Sep 17 00:00:00 2001 From: Akilan Date: Fri, 1 May 2026 15:47:18 +0100 Subject: [PATCH] saving current changes --- .../Benchmarks/Matrixmul/matrixmul.c | 38 +- .../CPrograms/Benchmarks/Richards/richards.c | 14 +- Tests/isa/CPrograms/link.ld | 5 +- Tests/isa/CPrograms/main.c | 14 +- Tests/isa/CPrograms/malloc.c | 107 +- Tests/isa/CPrograms/malloc_simulation.c | 97 + Tests/isa/testC | Bin 10184 -> 9688 bytes .../.gitignore | 1 + .../test.txt | 79402 ++-------------- 9 files changed, 9270 insertions(+), 70408 deletions(-) create mode 100644 Tests/isa/CPrograms/malloc_simulation.c create mode 100644 builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/.gitignore diff --git a/Tests/isa/CPrograms/Benchmarks/Matrixmul/matrixmul.c b/Tests/isa/CPrograms/Benchmarks/Matrixmul/matrixmul.c index 6dc30ce..5c54b13 100644 --- a/Tests/isa/CPrograms/Benchmarks/Matrixmul/matrixmul.c +++ b/Tests/isa/CPrograms/Benchmarks/Matrixmul/matrixmul.c @@ -20,10 +20,10 @@ void free(void * __capability ptr); void * __capability malloc(size_t size); /* Initializes vector or matrix, sequentially, with indices. */ -void init_seq(double * __capability a, const unsigned n_rows_a, const unsigned n_cols_a) { +void init_seq(int * __capability a, const unsigned n_rows_a, const unsigned n_cols_a) { for (size_t i = 0; i < n_rows_a; i++) { for (size_t j = 0; j < n_cols_a; j++) { - a[i*n_cols_a + j] = 2.0; + a[i*n_cols_a + j] = 2; } } } @@ -50,7 +50,7 @@ void init_seq(double * __capability a, const unsigned n_rows_a, const unsigned n It's also flat in memory, i.e., 1-D, but it should be looked at as a transpose of m, meaning, n_rows_t == n_cols_m, and n_cols_t == n_rows_m. The original matrix m stays intact. */ -double __capability * transpose(const double __capability *m, const unsigned n_rows_m, const unsigned n_cols_m, double __capability *t) { +int __capability * transpose(const int __capability *m, const unsigned n_rows_m, const unsigned n_cols_m, int __capability *t) { for (size_t i = 0; i < n_rows_m; i++) { for (size_t j = 0; j < n_cols_m; j++) { t[j*n_rows_m + i] = m[i*n_cols_m + j]; @@ -63,25 +63,27 @@ double __capability * transpose(const double __capability *m, const unsigned n_r /* Dot product of two arrays, or matrix product * Allocates and returns an array. * This variant doesn't transpose matrix b, and it's a lot slower. */ -double * __capability dot_simple(const double * __capability a, const unsigned n_rows_a, const unsigned n_cols_a,\ - const double * __capability b, const unsigned n_rows_b, const unsigned n_cols_b) { +int * __capability dot_simple(const int * __capability a, const unsigned n_rows_a, const unsigned n_cols_a,\ + const int * __capability b, const unsigned n_rows_b, const unsigned n_cols_b) { if (n_cols_a != n_rows_b) { // printf("#columns A must be equal to #rows B!\n"); // system("pause"); // exit(-2); + while(1); } - double *__capability c = malloc(n_rows_a * n_cols_b * sizeof(*c)); + int * __capability c = malloc(n_rows_a * n_cols_b * sizeof(*c)); if (c == NULL) { // printf("Couldn't allocate memory!\n"); // system("pause"); // exit(-1); + while(1); } for (size_t i = 0; i < n_rows_a; i++) { for (size_t k = 0; k < n_cols_b; k++) { - double sum = 0.0; + int sum = 0; for (size_t j = 0; j < n_cols_a; j++) { sum += a[i*n_cols_a + j] * b[j*n_cols_b + k]; } @@ -95,8 +97,8 @@ double * __capability dot_simple(const double * __capability a, const unsigned n /* Dot product of two arrays, or matrix product * Allocates and returns an array. * This variant transposes matrix b, and it's a lot faster. */ -double * __capability dot(const double __capability *a, const unsigned n_rows_a, const unsigned n_cols_a, \ - const double * __capability b, const unsigned n_rows_b, const unsigned n_cols_b) { +int * __capability dot(const int * __capability a, const unsigned n_rows_a, const unsigned n_cols_a, \ + const int * __capability b, const unsigned n_rows_b, const unsigned n_cols_b) { if (n_cols_a != n_rows_b) { // printf("#columns A must be equal to #rows B!\n"); @@ -104,9 +106,9 @@ double * __capability dot(const double __capability *a, const unsigned n_rows_a // exit(-2); } - double * __capability bt = malloc(n_rows_b * n_cols_b * sizeof(*b)); + int * __capability bt = malloc(n_rows_b * n_cols_b * sizeof(*b)); - double * __capability c = malloc(n_rows_a * n_cols_b * sizeof(*c)); + int * __capability c = malloc(n_rows_a * n_cols_b * sizeof(*c)); if ((c == NULL) || (bt == NULL)) { // printf("Couldn't allocate memory!\n"); @@ -118,7 +120,7 @@ double * __capability dot(const double __capability *a, const unsigned n_rows_a for (size_t i = 0; i < n_rows_a; i++) { for (size_t k = 0; k < n_cols_b; k++) { - double sum = 0.0; + int sum = 0; for (size_t j = 0; j < n_cols_a; j++) { sum += a[i*n_cols_a + j] * bt[k*n_rows_b + j]; } @@ -149,18 +151,18 @@ int main(void) { // srand(0); /* For measuring time */ - double t0, t1; + int t0, t1; - const unsigned scale = 14; + const unsigned scale = 20; const unsigned n_rows_a = 4 * scale; const unsigned n_cols_a = 3 * scale; const unsigned n_rows_b = 3 * scale; const unsigned n_cols_b = 2 * scale; - double __capability *a = malloc(n_rows_a * n_cols_a * sizeof(*a)); - double __capability *b = malloc(n_rows_b * n_cols_b * sizeof(*b)); - double __capability *c = NULL; - double __capability *d = NULL; + int __capability *a = malloc(n_rows_a * n_cols_a * sizeof(*a)); + int __capability *b = malloc(n_rows_b * n_cols_b * sizeof(*b)); + int __capability *c = NULL; + int __capability *d = NULL; if (!a || !b) { // printf("Couldn't allocate memory!\n"); diff --git a/Tests/isa/CPrograms/Benchmarks/Richards/richards.c b/Tests/isa/CPrograms/Benchmarks/Richards/richards.c index 616fcac..bcda04f 100644 --- a/Tests/isa/CPrograms/Benchmarks/Richards/richards.c +++ b/Tests/isa/CPrograms/Benchmarks/Richards/richards.c @@ -384,13 +384,13 @@ int bench() { wkq = pkt(wkq, I_DEVA, K_DEV); wkq = pkt(wkq, I_DEVA, K_DEV); - createtask(I_HANDLERA, 2000, wkq, S_WAITPKT, handlerfn, 0, 0); + // createtask(I_HANDLERA, 2000, wkq, S_WAITPKT, handlerfn, 0, 0); - wkq = pkt(0, I_DEVB, K_DEV); - wkq = pkt(wkq, I_DEVB, K_DEV); - wkq = pkt(wkq, I_DEVB, K_DEV); + // wkq = pkt(0, I_DEVB, K_DEV); + // wkq = pkt(wkq, I_DEVB, K_DEV); + // wkq = pkt(wkq, I_DEVB, K_DEV); - createtask(I_HANDLERB, 3000, wkq, S_WAITPKT, handlerfn, 0, 0); + // createtask(I_HANDLERB, 3000, wkq, S_WAITPKT, handlerfn, 0, 0); // wkq = 0; // createtask(I_DEVA, 4000, wkq, S_WAIT, devfn, 0, 0); @@ -434,9 +434,9 @@ int inner_loop(int inner) { int main(int argc, char* argv[]) { //INITREGULARALLOC(); - int iterations = 10; + int iterations = 1; int warmup = 0; - int inner_iterations = 10; + int inner_iterations = 1; // parse_argv(argc, argv, &iterations, &warmup, &inner_iterations); diff --git a/Tests/isa/CPrograms/link.ld b/Tests/isa/CPrograms/link.ld index 8b69c99..e64b21e 100644 --- a/Tests/isa/CPrograms/link.ld +++ b/Tests/isa/CPrograms/link.ld @@ -15,8 +15,5 @@ SECTIONS _end = .; __malloc_start = .; - . = . + 0x100000; - - /* End of uninitalized data segement */ - _end = .; + . = . + 0x10000; } \ No newline at end of file diff --git a/Tests/isa/CPrograms/main.c b/Tests/isa/CPrograms/main.c index 96f969f..fcb5b9f 100644 --- a/Tests/isa/CPrograms/main.c +++ b/Tests/isa/CPrograms/main.c @@ -63,35 +63,37 @@ void test() { // } int main(void) { - char * __capability a = malloc(30); + int * __capability a = malloc(30); char * __capability b = malloc(16); // if (!a || !b) return -1; - a[0] = 'A'; + a[0] = 1; a[1] = 'C'; b[0] = 'B'; + b[10] = 'D'; + // This will fault (out-of-bounds) // a[20] = 'X'; - if (a[1] != 'C') { + if (a[0] != 1) { while (1); } - if (b[0] != 'B') { + if (b[10] != 'D') { while (1); } - // free(b); + free(a); // b = NULL; // if (b[0] == 'B') { // while (1); // } - char * __capability c = malloc(16); + // char * __capability c = malloc(16); // if (c[0] != 'B') { // while (1); diff --git a/Tests/isa/CPrograms/malloc.c b/Tests/isa/CPrograms/malloc.c index ea50cdd..c7ea1ca 100644 --- a/Tests/isa/CPrograms/malloc.c +++ b/Tests/isa/CPrograms/malloc.c @@ -32,6 +32,23 @@ void tiny_free(void*); // void * __capability next; // } free_node_t; +static uintptr_t next_virtual = 0x10000000; + +uintptr_t compute_physical_base(size_t size) { + // 1. Determine the required alignment for this size in CHERI + size_t mask = cheri_representable_alignment_mask(size); + + // 2. Round up the current next_virtual to the required alignment + uintptr_t base = (next_virtual + ~mask) & mask; + + // 3. Ensure the length itself is representable + size_t representable_len = cheri_representable_length(size); + + // 4. Update the global pointer for the next call + next_virtual = base + representable_len; + + return base; +} // Add delta value for TLB translation @@ -51,46 +68,66 @@ static inline void * __capability add_delta(void * __capability cap, int offset) // Malloc wrapper +// Malloc wrapper +// void * __capability malloc(size_t size) { + +// uintptr_t raw = (uintptr_t)tiny_malloc(size); + +// // void *__capability cap = (void *__capability)raw; +// void *__capability cap = cheri_ddc_get(); + +// // // Set address from raw pointer +// cap = cheri_address_set(cap, raw); + +// int delta = 12; + +// delta = (delta + ALIGN - 1) & ~(ALIGN - 1); + +// cap = add_delta(cap, delta); + +// size_t aligned = cheri_representable_length(size); + +// cap = cheri_bounds_set(cap, aligned); + +// // // Align to 8 bytes (important for capability safety) +// // size = (size + 7) & ~7; + +// // if (bump + size > HEAP_SIZE) +// // return NULL; + +// // void * __capability base = cheri_ddc_get(); + +// // uintptr_t addr = (uintptr_t)(heap + bump); + +// // // Create capability to this region +// // void * __capability cap = cheri_address_set(base, addr); + +// // // Enforce bounds (this is the key CHERI feature) +// // cap = cheri_bounds_set(cap, size); + +// // // Hard-coded delta value +// // cap = add_delta(cap, 10); + +// // bump += size; + +// return cap; +// } + void * __capability malloc(size_t size) { + void * phys_ptr = tiny_malloc(size); + if (!phys_ptr) return NULL; - uintptr_t raw = (uintptr_t)tiny_malloc(size); + uintptr_t raw_phys = (uintptr_t)phys_ptr; + intptr_t p_base = compute_physical_base(size); + intptr_t delta = p_base - (intptr_t)raw_phys; - // void *__capability cap = (void *__capability)raw; - void *__capability cap = cheri_ddc_get(); + void * __capability cap = cheri_ddc_get(); + cap = cheri_address_set(cap, raw_phys); - // // Set address from raw pointer - cap = cheri_address_set(cap, raw); + cap = add_delta(cap, (int)delta); - int delta = 12; - - delta = (delta + ALIGN - 1) & ~(ALIGN - 1); - - cap = add_delta(cap, delta); - - size_t aligned = cheri_representable_length(size); - - cap = cheri_bounds_set(cap, aligned); - - // // Align to 8 bytes (important for capability safety) - // size = (size + 7) & ~7; - - // if (bump + size > HEAP_SIZE) - // return NULL; - - // void * __capability base = cheri_ddc_get(); - - // uintptr_t addr = (uintptr_t)(heap + bump); - - // // Create capability to this region - // void * __capability cap = cheri_address_set(base, addr); - - // // Enforce bounds (this is the key CHERI feature) - // cap = cheri_bounds_set(cap, size); - - // // Hard-coded delta value - // cap = add_delta(cap, 10); - - // bump += size; + size_t aligned_size = cheri_representable_length(size); + cap = cheri_bounds_set(cap, aligned_size); return cap; } diff --git a/Tests/isa/CPrograms/malloc_simulation.c b/Tests/isa/CPrograms/malloc_simulation.c new file mode 100644 index 0000000..b701b3e --- /dev/null +++ b/Tests/isa/CPrograms/malloc_simulation.c @@ -0,0 +1,97 @@ +#include +#include + +#define HEAP_SIZE 0x10000 + +extern uint8_t __malloc_start; + +static uint8_t* heap = &__malloc_start; + +typedef struct block { + size_t size; + int free; + struct block* next; +} block; + +static block* free_list; + +static intptr_t next_virtual = 0x10000000; + +intptr_t compute_virtual_base() { + intptr_t v = next_virtual; + next_virtual += 0x1000; // or size + return v; +} + +void mem_init() { + free_list = (block*)heap; + + free_list->size = HEAP_SIZE - sizeof(block); + free_list->free = 1; + free_list->next = NULL; +} + +void* my_malloc(size_t size) { + block* curr = free_list; + + while (curr) { + if (curr->free && curr->size >= size) { + + if (curr->size > size + sizeof(block)) { + block* newb = + (block*)((uint8_t*)curr + sizeof(block) + size); + + newb->size = curr->size - size - sizeof(block); + newb->free = 1; + newb->next = curr->next; + + curr->next = newb; + curr->size = size; + } + + curr->free = 0; + + // TODO: lift off delta to a earlier stage + + void* phys = (uint8_t*)curr + sizeof(block); + + // compute delta for this allocation + intptr_t delta = compute_virtual_base() - (intptr_t)phys; + + // apply hardware instruction assumption: + asm volatile("add_delta %0, %0, %1" + : "+r"(phys) + : "r"(delta)); + + return phys; + } + + curr = curr->next; + } + + return NULL; +} + +void my_free(void* ptr) { + if (!ptr) return; + + // delta is guaranteed 0 → treat pointer as physical + block* b = (block*)((uint8_t*)ptr - sizeof(block)); + + b->free = 1; + + // coalesce adjacent free blocks (pure physical heap logic) + block* curr = free_list; + + while (curr && curr->next) { + if (curr->free && curr->next->free) { + curr->size += sizeof(block) + curr->next->size; + curr->next = curr->next->next; + } else { + curr = curr->next; + } + } +} + + + diff --git a/Tests/isa/testC b/Tests/isa/testC index 46e9c88c1dfdeaafbe5afff71d0dcc81cef2486c..d00777fa1a39101ff359867fc589b90d3c6da884 100755 GIT binary patch delta 1595 zcmZ`(UuauZ82?UkPns5NZF7VD!!{bXVR6ceAa{_a>6HfCBu(z> z`eLGMqz@{qhvHs@Ig&ky58F!Ji({KG*z-UTpSHnp4+?u2qsHXwckVgaMDT-i&hPtu z-*>+6eCOPI=fp2>of`_C4}&8V=V_P(1?P5X+xjRpbC+`{trb+E6I?tTYJ5UbN%`Na zbc0^jORbAJp7b^NyTB8Qt)xy(NyGvJWL$3hG59Z^GH1%oul~qq;V6O}$5sp;t z^~Beh=eP3BuJEyHV@7KCIx(Vw(alN%_uAvg2qeHqV~SCtm-f0MO2bDr#ZVCIO2Y`$ z&^X=Fn+C1b(>=S810XqUmKXqzufGNcyUxcTs4dGR>!;=nfqP=-|d-Fc> z&5L=LmB4M^U;XUK#mD7d=`Ry&s)$jVeYdc5=LiP9VDmoaN^q~uJ*G6nqhec8YxyY_ zgDI89*|Ckr3%r0jzZ49qFpnn)4t5j~YIsd2wAKqeL`uiPNyTPvd2RNkq zb@r=&0iloT*LLE8DA_ql4t211h^I$|GJk$ECvhrdis>~V$C+Q7@+Qxum&`&Y#!hI~ zzS&InL$mOzHaq)7MPvAK`&d5IOT26~6ddWsa00GpkKfBTMd`=kLdyY{$n%oJ z0u1q}(l}}=T2ab;YRM4<`;f;kqs+M<_=FP2!TABnA9h%PqmrK|!v9Cfzb*M=GW)RP z`C)ON5_HIb_oQJ-1{7p~f+yl);oyna6p`SRQ!~KF$ajMqRQb)fj(yJIUEuu>{|)la zft|Jwp(f>fT%Q|SEUr<@JY%u_`im3M;`)k}T7YPAsc01h5-Y5vGTCSvm*wSL8bKCg zl53fQbvm`omIwQeB#Tz6U^#wZnMIDcD|}EeO-Scf@~17c6_8v=6-}@*+4ZFGVw;1* zzNA#-PDwMn$lfJKxAF@6TtDEtOWAjNe_tC`%v*zhI3e=!l?NsIBf@JS#TM2P)12vp$|=&3!{(g!yYzh8kUcTz+9FssjZLw{^#5y zOV?Sm!PwJ1aPK+i_y0V<|GC#U%6U2Vy=PpC!en!?zcXuAA}mTbv_k>WtLUO^n5now z#M+sgvAhSER}*sk{W%*TBT-Mjn6IHwvPQhWdY zUZ0QK$)5Ybt&xs3_`!8E#p6kZ2lNg52k1FshXIEHhXIEHhXIEHhXIEHhXIEHhXIEH zhk^em1Ak`B^*fiB&Go(KI(l|Odjr95mM-?~ojp6I9`yeTF=SnjC+h<=7QB$0Ft0Ebv#=;KGhxcf?Z*E^O^R zH{_}Q{_f4=dxq~cEY$$_v-0`criiC{Dep34`YWZ86K$2gdnIOzdf$kpc8Z9c_9CZ2 znbUYvPMW%&(|EP(LWG5p)t=Cu3gs@=d{sTS-%~lfN&VyDyEnI=+h4AHcK4=h&!Eh7 zyoyW_A-D4KDoJTgjTQb%@*r2U^Pku9V`eW_qHJ!v-FJ)m{JX*5uFJ4lt|4lzf3c^n zn?0p|;_7+fAIiXD&-2~U{zWx#ZE`H7{r_P^lRf@WD-zxAe|m{nuSp$k+dFga zNV&4*TZq_p<4+yeILmxrQ4PyAv9GSWL=B1caqO#i7P{1x0~6izUkL8k>+=!qPpTAr zkZvHBJVHBD^E5m}%2oI7a?Q$e1@Wt5of6ajX7~EbH6Fu54HNcv!$i1?rkDmDH?Mt^xK3WIy@n|e*a^@6bW0Wer znqwCgH)LmH=NA{x2N!x(f#N+7DX(H&5qsy84=IXZyj=C_+fb(~UF&mtgTN0Yv#7p^ z!@NQ+(T~++ipQ6=uX+t=SLeSVOCGrfi*K&``Nq%vV2;lX#9yTm`428M>?$<+nNB{+ zYu5OBj!kw7t8E|W@N*{Rv89{g8Hl~hpMmOY`g;pW56`B}S_M3L;0ZB@msb1c-hlq= zbFtqLqI5&HW@XRWZRy>3TY3j) zf}0laB{yaLx_bT6yiN?y>+Yd)CA?rgC5T2j+xVl()ox5alM3Ly)BH9dT<^AaOO2Sh zg6AlTi*<=A8;gGI6~Tw6CaQe#;q|$!a)&M|U}LcAqxVa7UZ)J*7GlMumi zW7Rym6$Px(icuqCVC4YbA~fIVEz0Ecwf_6Ea%O@lrxc~9!^L*sZ|+uH7w*;TGxW!Q ztTQxzR+)E=b?~37Nj{A0HsqfQdDJd{5%`6#>UGkCy=Ir60{kxI$Ax@@{hPq=K|Unp zE%7yAAK>a-t=B6;-eOM><@gs|H=y$h0b`vlIwU9CLu>W=s zrgK?sV1Fcnb{t7nZ&q$2V1}6{DHLp0wc|K)){kA$O}E{9}aY z`GJM=Z$EO)o5Cb65sClR=4U4aUl+I2(;8R$d8Dls?}uPBJjpuB^B@DjAHjO1KL3UU z_Ns-;b@6XoU{B#9KR$Vm1aoTN$F;d>|49Eo1Wx`X|NJ`~SQ3{H`tmu%l((PY?t?yB ziEgqLFd#p2KYVHl&RDptBma&ER<>|iNBRb*b{-e`k-YJ5YG4Z%F83k-_Xx1(afv*| zxfx7(qd4S8){B3;lO&-RvPLnOWTPyjPfzEP80x81JY`Iqx&_5eqi6y*GkIpFv!~-z z1;b$RxG>2%RtM~rNWWlm0;@lkVT9W9!A!L;xhDIdj1PiKW+;gF?rCS$?k>5Qo- z(3=I(ACn`~IAyY+aSW05i~)_5j$DJqM6t+%{N)(bO|y_roJ8V`USb&|3zz?c)&n0@ z?WVIvCGOTbP?X)oXN{ZvoKY_%WKaJzq9)&K`7L68if<(`rn}si68R1Wq=Gk}X!8B1 ziK$)RJ`Y2UFlpa-zASrtzIJ!SgJu7kwJ^$?D3$qdwUpb@%e7k&?_S&`W^Xlv7|Xa4-i*Qh?7y_^4@*U>x7+^< DZ5-L8 diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/.gitignore b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/.gitignore new file mode 100644 index 0000000..2211df6 --- /dev/null +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/.gitignore @@ -0,0 +1 @@ +*.txt diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt index 2223ef0..022e314 100644 --- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt @@ -4,26 +4,23 @@ make[1]: 'elf_to_hex' is up to date. make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex' ../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file -Section .text : addr 80000000 to addr 800016f8; size 0x 16f8 (= 5880) bytes -Section .srodata.cst8 : addr 800016f8 to addr 80001788; size 0x 90 (= 144) bytes -Section .rodata : addr 80001788 to addr 800017c0; size 0x 38 (= 56) bytes -Section .eh_frame : addr 800017c0 to addr 80001ad8; size 0x 318 (= 792) bytes -Section .sdata : addr 80002000 to addr 80002010; size 0x 10 (= 16) bytes -Section .sbss : addr 80102010 to addr 80102058; size 0x 48 (= 72) bytes +Section .text : addr 80000000 to addr 800005be; size 0x 5be (= 1470) bytes +Section .sdata : addr 80011000 to addr 80011010; size 0x 10 (= 16) bytes +Section .sbss : addr 80011010 to addr 80011018; size 0x 8 (= 8) bytes Section .riscv.attributes: Ignored Section .comment : Ignored Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols Writing symbols to: symbol_table.txt No 'exit' label found No 'tohost' symbol found -Section .strtab : Ignored Section .shstrtab : Ignored +Section .strtab : Ignored Min addr: 80000000 (hex) -Max addr: 80102057 (hex) +Max addr: 80011017 (hex) Writing mem hex to file 'Mem.hex' Subtracting 0x80000000 base from addresses ./exe_HW_sim +v1 +tohost -Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 33027 to 33554430. +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2177 to 33554430. 1: top.soc_top.rl_reset_start_initial ... calling cycle calling cycle @@ -1225,10 +1222,10 @@ calling cycle [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000086 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000044 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 0: r 46 <= 0000000000020000000000001fffff44000000 [RFile] wr_ 1: r 45 <= 40000000200000000000ffff1fffff44000000 @@ -1240,20 +1237,18 @@ calling cycle [RFile] wr_ 0: r 48 <= 0000000020000400000000001fffff44000000 instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1156 calling cycle -[RFile] wr_ 0: r 4a <= 0000000020000404000000001fffff44000000 +[RFile] wr_ 0: r 4a <= 0000000020000004000000001fffff44000000 [RFile] wr_ 1: r 49 <= 0000000020000400000000001fffff44000000 instret:8 PC:0x1ffff000000000000000000008000000a instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1157 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 1: r 4b <= 0000000020000006000000001fffff44000000 -[ALU redirect - 1] 'h1ffff0000000000000000000080001096; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } - 11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[ALU redirect - 1] 'h1ffff0000000000000000000080000054; 'h0; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1158 -instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00001097 iType:Auipc [doCommitNormalInst [1]] 1158 +instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1158 calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h05, t: 'h0b } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; calling cycle -instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x086080e7 iType:Jr [doCommitNormalInst [0]] 1160 +instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x044080e7 iType:Jr [doCommitNormalInst [0]] 1160 calling cycle calling cycle calling cycle @@ -1305,555 +1300,599 @@ calling cycle calling cycle calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffb0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000048, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000050 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000040, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 12640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000048, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 12650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000048, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff8 After delta: vaddr = 0x80000ff8 - 12650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000040, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 4c <= 00000000200003ec000000001fffff44000000 - 12660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000048, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 4c <= 00000000200003f0000000001fffff44000000 + 12150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 12660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000040, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000ff0 After delta: vaddr = 0x80000ff0 - 12660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 12150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000e8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle [RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000 - 12670 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } - 12670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000040, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 12160 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 12160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 12670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 - 12670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:12 PC:0x1ffff0000000000000000000080001096 instr:0x0000715d iType:Alu [doCommitNormalInst [0]] 1267 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff52 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 - 12680 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } - 12680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 12680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 12160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fec After delta: vaddr = 0x80000fec - 12680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:13 PC:0x1ffff0000000000000000000080001098 instr:0x0000e486 iType:St [doCommitNormalInst [0]] 1268 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:12 PC:0x1ffff0000000000000000000080000054 instr:0x00007139 iType:Alu [doCommitNormalInst [0]] 1216 calling cycle -[RFile] wr_ 0: r 53 <= 0000000000000000c00000001fffff44000000 - 12690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9098 } - 12690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 0: r 50 <= 0000000000000000000000001fffff44000000 + 12170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 12170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fec, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 12690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe8 -After delta: vaddr = 0x80000fe8 - 12690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 12690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } -instret:14 PC:0x1ffff000000000000000000008000109a instr:0x0000e0a2 iType:St [doCommitNormalInst [0]] 1269 -instret:15 PC:0x1ffff000000000000000000008000109c instr:0x00000880 iType:Alu [doCommitNormalInst [1]] 1269 +instret:13 PC:0x1ffff0000000000000000000080000056 instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 1217 calling cycle -[RFile] wr_ 1: r 55 <= 000000002000082b800000001fffff44000000 - 12700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } - 12700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000003 o: 'h0000000000000003 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } - 12700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 12700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 0: r 52 <= 0000000000000007800000001fffff44000000 +[RFile] wr_ 1: r 53 <= 0000000020000019000000001fffff44000000 + 12180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fec o: 'h0000000080000fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fec, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8056 } + 12180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } +instret:14 PC:0x1ffff0000000000000000000080000058 instr:0x0000f822 iType:St [doCommitNormalInst [0]] 1218 +instret:15 PC:0x1ffff000000000000000000008000005a instr:0x00000080 iType:Alu [doCommitNormalInst [1]] 1218 +calling cycle +[RFile] wr_ 1: r 54 <= 000000002000001b000000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000014c; 'h0; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } + 12190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 12190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } + 12190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:16 PC:0x1ffff000000000000000000008000005c instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1219 +instret:17 PC:0x1ffff000000000000000000008000005e instr:0xfea42623 iType:St [doCommitNormalInst [1]] 1219 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0a, t: 'h14 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 12210 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:18 PC:0x1ffff0000000000000000000080000062 instr:0x00004579 iType:Alu [doCommitNormalInst [0]] 1221 +instret:19 PC:0x1ffff0000000000000000000080000064 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1221 +calling cycle +instret:20 PC:0x1ffff0000000000000000000080000068 instr:0x0e8080e7 iType:Jr [doCommitNormalInst [0]] 1222 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 13760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 13770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 13770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 13770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8058 } + 13780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } +calling cycle + 13790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } + 13790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 13790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 13790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h805e } + 13800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +calling cycle + 13810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 13810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } + 13810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 13810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 13810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 14340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000fb8 After delta: vaddr = 0x80000fb8 - 12700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:16 PC:0x1ffff000000000000000000008000109e instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 1270 -instret:17 PC:0x1ffff00000000000000000000800010a0 instr:0xfca43023 iType:St [doCommitNormalInst [1]] 1270 + 14340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 56 <= 0000000020000800000000001fffff44000000 - 12710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe8, check_high: 'h00000000080000fec, check_inclusive: True } }, specBits: 'h000 } - 12710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[RFile] wr_ 1: r 55 <= 00000000200003d4000000001fffff44000000 + 14350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000006c o: 'h000000008000006c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 12710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 14350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -instret:18 PC:0x1ffff00000000000000000000800010a4 instr:0xfea42623 iType:St [doCommitNormalInst [0]] 1271 -instret:19 PC:0x1ffff00000000000000000000800010a8 instr:0x0000450d iType:Alu [doCommitNormalInst [1]] 1271 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 14350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h02, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000102 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 12720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 12720 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 12720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 58 <= 00000000200003f0000000001fffff44000000 + 14360 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 14360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc -instret:20 PC:0x1ffff00000000000000000000800010aa instr:0xfea42423 iType:St [doCommitNormalInst [0]] 1272 -instret:21 PC:0x1ffff00000000000000000000800010ae instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 1272 -calling cycle - 12730 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 12730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h90ba } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 12730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } -instret:22 PC:0x1ffff00000000000000000000800010b2 instr:0xf5250513 iType:Alu [doCommitNormalInst [0]] 1273 -instret:23 PC:0x1ffff00000000000000000000800010b6 instr:0xfaa43c23 iType:St [doCommitNormalInst [1]] 1273 -calling cycle - 12740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 12740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } - 12740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 12760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h1a, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002da }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle -calling cycle -calling cycle -[RFile] wr_ 1: r 5a <= 000000002000042f800000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5b <= 0000000020000431800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 14270 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9098 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h909a } - 14290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h909a } -calling cycle - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h909a } - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h909a } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90a0 } - 14310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a0 } -calling cycle - 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a0 } - 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fec, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90a4 } - 14330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a4 } -calling cycle - 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a4 } - 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fec, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90a4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90aa } - 14350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90aa } -calling cycle - 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90aa } - 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90aa } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 14360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90b6 } - 14370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } -calling cycle - 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } - 14380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 14400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 14790 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002000, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90ba } - 14800 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 14800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 14810 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000000000000c00000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:24 PC:0x1ffff00000000000000000000800010ba instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 1483 -calling cycle -[RFile] wr_ 0: r 59 <= 0000000000000006000000001fffff44000000 -calling cycle -instret:25 PC:0x1ffff00000000000000000000800010bc instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 1485 -instret:26 PC:0x1ffff00000000000000000000800010be instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1485 -calling cycle -instret:27 PC:0x1ffff00000000000000000000800010c2 instr:0x2da080e7 iType:Jr [doCommitNormalInst [0]] 1486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 14360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 15160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 14360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:21 PC:0x1ffff000000000000000000008000014c instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 1436 calling cycle -[RFile] wr_ 1: r 5c <= 00000000200003d4000000001fffff44000000 - 15170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800010c6 o: 'h00000000800010c6 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } + 14370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 14370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 15170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 14370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 15170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1d6 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:22 PC:0x1ffff000000000000000000008000014e instr:0x0000f486 iType:St [doCommitNormalInst [0]] 1437 calling cycle -[RFile] wr_ 1: r 5f <= 00000000200003ec000000001fffff44000000 - 15180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 15180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } +[RFile] wr_ 0: r 5b <= 0000000020000057000000001fffff44000000 + 14380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h814e } + 14380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 15180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 14380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } +instret:23 PC:0x1ffff0000000000000000000080000150 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 1438 +instret:24 PC:0x1ffff0000000000000000000080000152 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 1438 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000078, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0d, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 0000000020000059000000001fffff44000000 +[ALU redirect - 1] 'h1ffff000000000000000000008000025e; 'h0; InstTag { way: 'h0, ptr: 'h0e, t: 'h1c } + 14390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 14390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8158 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 14390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000078, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0d, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:25 PC:0x1ffff0000000000000000000080000154 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 1439 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0e, t: 'h1c } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 14410 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000fb8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 14410 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 0000000000000007800000001fffff44000000 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:26 PC:0x1ffff0000000000000000000080000158 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1443 +instret:27 PC:0x1ffff000000000000000000008000015c instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 1443 +calling cycle +instret:28 PC:0x1ffff0000000000000000000080000160 instr:0x102080e7 iType:Jr [doCommitNormalInst [0]] 1444 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 15170 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 15180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15180 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8150 } + 15190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } +calling cycle + 15200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } + 15200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8154 } + 15210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +calling cycle + 15220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } + 15220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 15220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 15220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 15540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 15180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:28 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1518 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 15540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15190 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 15190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 5d <= 00000000200003bc000000001fffff44000000 + 15550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000164 o: 'h0000000080000164 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 15190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 15550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 -instret:29 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1519 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 15550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h139 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 62 <= 0000000000000001c00000001fffff44000000 - 15200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 15200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 60 <= 00000000200003d4000000001fffff44000000 + 15560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 15560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc -instret:30 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1520 -instret:31 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1520 + 15560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 15560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:29 PC:0x1ffff000000000000000000008000025e instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 1556 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 15210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } -instret:32 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1521 + 15570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 15570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 +instret:30 PC:0x1ffff0000000000000000000080000260 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 1557 calling cycle - 15220 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000006000000001fffff44000000 +[RFile] wr_ 0: r 63 <= 0000000000000001c00000001fffff44000000 + 15580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8260 } + 15580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 15580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } +instret:31 PC:0x1ffff0000000000000000000080000262 instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 1558 +instret:32 PC:0x1ffff0000000000000000000080000264 instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 1558 calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 15590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 15590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h826a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } + 15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:33 PC:0x1ffff0000000000000000000080000266 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 1559 calling cycle -instret:33 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 1524 -instret:34 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 1524 + 15600 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 0000000000000007800000001fffff44000000 +calling cycle + 15610 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f48, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +instret:34 PC:0x1ffff000000000000000000008000026a instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 1562 +instret:35 PC:0x1ffff000000000000000000008000026e instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 1562 calling cycle calling cycle -instret:35 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1526 -instret:36 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 1526 +instret:36 PC:0x1ffff0000000000000000000080000270 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 1564 +instret:37 PC:0x1ffff0000000000000000000080000274 instr:0x0120006f iType:J [doCommitNormalInst [1]] 1564 calling cycle calling cycle calling cycle @@ -1869,43 +1908,752 @@ calling cycle calling cycle calling cycle calling cycle - 15410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000fb8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } calling cycle - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90b6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 15430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } calling cycle - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 15450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } calling cycle - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 16120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 0000000000000000000000001fffff44000000 + 16130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 16130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8286 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 16140 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000007800000001fffff44000000 + 16140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 16150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffd6c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 16160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:38 PC:0x1ffff0000000000000000000080000286 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1616 +instret:39 PC:0x1ffff000000000000000000008000028a instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 1616 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 68 <= 3ffffffffffffff88fff00001fffff44000000 + 16170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h829c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 16170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h15d }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000000000000800000001fffff44000000 + 16180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 16180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 16180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:40 PC:0x1ffff000000000000000000008000028c instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 1618 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000000000008000000001fffff44000000 + 16190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 16190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 16190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:41 PC:0x1ffff000000000000000000008000028e instr:0x0000899d iType:Alu [doCommitNormalInst [0]] 1619 +calling cycle + 16200 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000ef8, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[RFile] wr_ 0: r 70 <= 00000000200044a9000000001fffff44000000 +[RFile] wr_ 1: r 6b <= 000000000000000a000000001fffff44000000 + 16200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h002 } + 16200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h82b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 16200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000028 o: 'h0000000000000028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 16200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 16200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } +instret:42 PC:0x1ffff0000000000000000000080000290 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1620 +calling cycle +[RFile] wr_ 1: r 71 <= 0000000020004404000000001fffff44000000 + 16210 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 16210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 16210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } + 16210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:43 PC:0x1ffff0000000000000000000080000292 instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 1621 +calling cycle + 16220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +instret:44 PC:0x1ffff0000000000000000000080000294 instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 1622 +instret:45 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1622 +calling cycle + 16230 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f28, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16350 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f48, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16360 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8262 } + 16370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } +calling cycle + 16380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } + 16380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 16380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 16380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8266 } + 16390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } +calling cycle + 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } + 16400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 16970 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000ef8, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 16980 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 16980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 16990 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000000000000001fffff44000000 + 16990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 17000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 +calling cycle + 17010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 17280 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f28, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } + 17290 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } + 17290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +calling cycle + 17300 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8294 } + 17310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8294 } +calling cycle + 17320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8294 } + 17320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8294 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 17320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 17960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffd6c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 17970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 17980 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 17980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h829c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 17980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 17980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h15d }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 00000000200044a9000000001fffff44000000 + 17990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 17990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 17990 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 17990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 17990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000020004404000000001fffff44000000 + 18000 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 000000000000000a000000001fffff44000000 + 18000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 18000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc0e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 18010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 18020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h82b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 18020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000028 o: 'h0000000000000028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:46 PC:0x1ffff000000000000000000008000029c instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 1802 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 78 <= 00000000200003d4000000001fffff44000000 + 18030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 18030 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 74 <= 0000000020004404000000001fffff44000000 + 18030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h206 }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 00000000200044fe800000001fffff44000000 + 18040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011010 +After delta: vaddr = 0x80011010 + 18040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:47 PC:0x1ffff00000000000000000000800002a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1804 +instret:48 PC:0x1ffff00000000000000000000800002a4 instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 1804 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 0000000020004402000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a0 } + 18050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011010, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 18050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 18050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:49 PC:0x1ffff00000000000000000000800002a8 instr:0xd6c50513 iType:Alu [doCommitNormalInst [0]] 1805 +instret:50 PC:0x1ffff00000000000000000000800002ac instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1805 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18060 : [doFinishMem] DTlbResp { resp: <'h0000000080011010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011010, check_high: 'h00000000080011018, check_inclusive: True } }, specBits: 'h000 } + 18060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080011010, shiftedBE: tagged DataMemAccess , pcHash: 'h82b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 18060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +instret:51 PC:0x1ffff00000000000000000000800002b0 instr:0x0040006f iType:J [doCommitNormalInst [0]] 1806 +calling cycle + 18070 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82ac } + 18070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h8402 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 18070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 18070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } +instret:52 PC:0x1ffff00000000000000000000800002b4 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1807 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffbe6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h002 } + 18080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8408 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 18080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 18080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 18090 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080011010, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 18090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + 18090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + 18090 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 18090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ac } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 18100 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 000000000000000a000000001fffff44000000 + 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ac } + 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ac } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 0b <= 0000000020004508800000001fffff44000000 + 18110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 18110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 0000000020004402000000001fffff44000000 + 18120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 18120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 18130 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h003 } + 18130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h842a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 18130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } +calling cycle + 18140 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h003 } + 18140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h8430 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 18140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 18140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } +calling cycle + 18150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h003 } + 18150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8432 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 18150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h2 + 18150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8432 } +calling cycle + 18160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8432 } + 18160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8432 } + 18160 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 18160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 18170 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 000000000000000a000000001fffff44000000 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 18570 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080011010, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +calling cycle + 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 18580 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 18580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +calling cycle + 18590 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 0000000000000000000000001fffff44000000 + 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 18590 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 18590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080011010, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18600 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000020000400000000001fffff44000000 + 18600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 18600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 18600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 18600 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } + 18600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18610 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 40 <= 0000000020000400000000001fffff44000000 + 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 18610 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } + 18610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:53 PC:0x1ffff00000000000000000000800002b8 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1861 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18620 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 01 <= 0000000020000400000000001fffff44000000 + 18620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 +calling cycle +[RFile] wr_ 1: r 7c <= 3fffffffffffffd40fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 18630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:54 PC:0x1ffff00000000000000000000800002ba instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 1863 +instret:55 PC:0x1ffff00000000000000000000800002bc instr:0x13c0006f iType:J [doCommitNormalInst [1]] 1863 +calling cycle +[RFile] wr_ 1: r 7d <= 3fffffffffffffcc0fff00001fffff44000000 + 18640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } + 18640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 +instret:56 PC:0x1ffff00000000000000000000800003f8 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 1864 +instret:57 PC:0x1ffff00000000000000000000800003fa instr:0x00011597 iType:Auipc [doCommitNormalInst [1]] 1864 +calling cycle +[RFile] wr_ 0: r 46 <= 000000002000040a000000001fffff44000000 + 18650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:58 PC:0x1ffff00000000000000000000800003fe instr:0xc0e58593 iType:Alu [doCommitNormalInst [0]] 1865 +instret:59 PC:0x1ffff0000000000000000000080000402 instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 1865 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18660 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h000 } +instret:60 PC:0x1ffff0000000000000000000080000404 instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 1866 +instret:61 PC:0x1ffff0000000000000000000080000406 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 1866 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:62 PC:0x1ffff0000000000000000000080000408 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1867 +instret:63 PC:0x1ffff000000000000000000008000040c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 1867 +calling cycle +instret:64 PC:0x1ffff0000000000000000000080000410 instr:0x0120006f iType:J [doCommitNormalInst [0]] 1868 +instret:65 PC:0x1ffff0000000000000000000080000422 instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 1868 +calling cycle +instret:66 PC:0x1ffff0000000000000000000080000426 instr:0xbe650593 iType:Alu [doCommitNormalInst [0]] 1869 +instret:67 PC:0x1ffff000000000000000000008000042a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 1869 +calling cycle +instret:68 PC:0x1ffff000000000000000000008000042c instr:0xfca43823 iType:St [doCommitNormalInst [0]] 1870 +instret:69 PC:0x1ffff0000000000000000000080000430 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 1870 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h842c } + 18710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842c } +instret:70 PC:0x1ffff0000000000000000000080000432 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 1871 +instret:71 PC:0x1ffff0000000000000000000080000436 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 1871 +calling cycle + 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842c } + 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842c } [Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:72 PC:0x1ffff0000000000000000000080000438 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1872 +instret:73 PC:0x1ffff000000000000000000008000043a instr:0x0040006f iType:J [doCommitNormalInst [1]] 1872 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 15470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080011008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8438 } + 18730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080011008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8438 } calling cycle - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 15480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080011008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8438 } + 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080011008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8438 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 18740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle calling cycle @@ -1923,8620 +2671,7183 @@ calling cycle calling cycle calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 18920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 15790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 18930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 18930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle - 15800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } + 18940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 0000000000000000000000001fffff44000000 - 15810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 15810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93c0 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93c0 } - 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080000f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93c0 } - 15820 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } } - 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 15820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 15830 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000006000000001fffff44000000 - 15830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 18940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 15840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 18950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 18950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h843e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 18950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 18950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h843e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 15850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 15850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 15850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } -instret:37 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 1585 -instret:38 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 1585 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1fa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 67 <= 3ffffffffffffffa0fff00001fffff44000000 - 15860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 15860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 15860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 18960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 18960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8442 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h843e } + 18960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h843e } + 18960 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 18960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 15860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 18960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8442 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 68 <= 0000000000000000000000001fffff44000000 -[RFile] wr_ 1: r 70 <= 0000000020040814000000001fffff44000000 - 15870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 18970 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 45 <= 000000000000000a000000001fffff44000000 + 18970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 15870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } + 18970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8442 } + 18970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8442 } + 18970 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } + 18970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 18980 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8448 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 18980 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4a <= 0000000020000400000000001fffff44000000 + 18980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 15870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:39 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 1587 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 18980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 18980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8448 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 15880 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080000f58, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -[RFile] wr_ 0: r 69 <= 0000000000000006000000001fffff44000000 - 15880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 15880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 18990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 15880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 18990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 18990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8448 } + 18990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 18990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8448 } + 18990 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 18990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 18990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 -instret:40 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [0]] 1588 +Before delta: vaddr = 0x80001000 +After delta: vaddr = 0x80001000 + 18990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:74 PC:0x1ffff000000000000000000008000043e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 1899 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 6a <= 0000000000000008000000001fffff44000000 - 15890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 15890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 15890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } + 19000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 19000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8456 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19000 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 0000000020000400000000001fffff44000000 + 19000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000028 o: 'h0000000000000028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc -instret:41 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 1589 -calling cycle - 15900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 15900 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000020040814000000001fffff44000000 - 15900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:42 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 1590 -calling cycle - 15910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 19000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 -instret:43 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 1591 -instret:44 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1591 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 19000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } +instret:75 PC:0x1ffff0000000000000000000080000442 instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 1900 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 15920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } + 19010 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 } + 19010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 15920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -calling cycle - 15930 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 15930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 15930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 - 15930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -calling cycle - 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 15940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 15960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080102050, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 16650 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080000f58, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 16660 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 16660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 -calling cycle - 16670 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 3f810d60ffb10940cfe000001fffff44000000 - 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit - 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 16670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 16670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 16680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 19010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 19010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 19010 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 19010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 19010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 16690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfe043583fec42503 o: 'hfe043583fec42503 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +[RFile] wr_ 0: r 53 <= 00000000200003d4000000001fffff44000000 + 19020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 19020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h845a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19020 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000000000000000000001fffff44000000 + 19020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 17290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080102050, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 17300 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 17300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 17310 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 19020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 19020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } +instret:76 PC:0x1ffff0000000000000000000080000446 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1902 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle - 18350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +[RFile] wr_ 1: r 4e <= 0000000020000402000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8446 } + 19030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h845c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 18360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 18360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h1fa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 6f <= 00000000200408f7800000001fffff44000000 - 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 18370 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 18370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 18370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 0000000020040814000000001fffff44000000 - 18380 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 18380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 18380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 18390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 18400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 18400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:45 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 1840 -calling cycle -[RFile] wr_ 0: r 77 <= 00000000200003ec000000001fffff44000000 - 18410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 18410 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 73 <= 0000000020040814000000001fffff44000000 - 18410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 000000002000094d000000001fffff44000000 - 18420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 18420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:46 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 1842 -instret:47 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 1842 -calling cycle -[RFile] wr_ 0: r 79 <= 0000000020000802000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 18430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 18430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:48 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 1843 -instret:49 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 1843 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18440 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 18440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -instret:50 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 1844 -calling cycle - 18450 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 18450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 18450 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 18450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } -instret:51 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 1845 -calling cycle - 18460 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000000000000000000001fffff44000000 - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 18460 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 18460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 18460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 18470 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000804000000001fffff44000000 - 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 18470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:52 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 1848 -calling cycle -calling cycle -[RFile] wr_ 1: r 7b <= 3ffffffffffffbe80fff00001fffff44000000 -instret:53 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 1850 -instret:54 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 1850 -calling cycle -instret:55 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 1851 -instret:56 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 1851 -calling cycle -instret:57 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 1852 -instret:58 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 1852 -calling cycle -instret:59 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 1853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 18930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -calling cycle -[RFile] wr_ 1: r 7c <= 3ffffffffffffbe00fff00001fffff44000000 - 18940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 18940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 18940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } -calling cycle - 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 18950 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 18950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:60 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [0]] 1895 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 18960 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 18980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:61 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 1898 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 18990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 18990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 0000000020000802000000001fffff44000000 - 19000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 19000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:62 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [0]] 1900 -instret:63 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [1]] 1900 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19010 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 19010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 19010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:64 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [0]] 1901 -instret:65 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [1]] 1901 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19020 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 19020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 19020 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 19020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 19030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19030 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000804000000001fffff44000000 - 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 19030 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 19030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 19030 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 19030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0b6 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19040 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000804000000001fffff44000000 - 19040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } + 19040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 19040 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000020000059000000001fffff44000000 + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 19040 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 19040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 19050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19050 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000000000008000000001fffff44000000 - 19050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 19050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:66 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1905 -calling cycle - 19060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 19060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 19060 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } - 19060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 19070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 19070 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 0000000000000008000000001fffff44000000 - 19070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 -instret:67 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 1907 -calling cycle -[RFile] wr_ 1: r 43 <= 000000002000080c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 19080 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 45 <= 0000000020000804000000001fffff44000000 - 19080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19090 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:68 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 1909 -calling cycle -instret:69 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 1910 -instret:70 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 1910 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:71 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1911 -instret:72 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1911 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 19120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:73 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 1912 -calling cycle - 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:74 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [0]] 1913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002010 -After delta: vaddr = 0x80002010 - 19520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 19530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002010, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19540 : [doFinishMem] DTlbResp { resp: <'h0000000080002010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002010, check_high: 'h00000000080002018, check_inclusive: True } }, specBits: 'h000 } - 19540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 19550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 19550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9582 } -instret:75 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 1955 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002010, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 19560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9582 } - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9582 } - 19560 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 19560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19570 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000020000804000000001fffff44000000 - 19570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 19570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19580 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 19580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 19580 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 0: r 50 <= 00000000200003ec000000001fffff44000000 - 19590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 19590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19590 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 196b3f810d60ffb1065a00001fffff44000000 - 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 19590 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 19590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 19590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:76 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 1959 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4d <= 0000000020000806000000001fffff44000000 - 19600 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000020000431800000001fffff44000000 - 19600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002018 o: 'h0000000080002018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 19600 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 19600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff74 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 19610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 19610 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000020000400000000001fffff44000000 - 19610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:77 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 1961 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 19620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 -instret:78 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1962 -instret:79 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 1962 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 196b3f810d60ffb1065a00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 19630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 19630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 19630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000020040833000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 19640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 19640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h90c8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 19640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 19640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102040 -After delta: vaddr = 0x80102040 - 19640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } -calling cycle -calling cycle - 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } - 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } - 19660 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 19660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 19670 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 20230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 20240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 20250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 20250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 20260 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 20260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 20260 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 20260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 1: r 50 <= 00000000200003ec000000001fffff44000000 - 20270 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 20270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20270 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000020000806000000001fffff44000000 - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 20270 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 20270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20280 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000020000431800000001fffff44000000 - 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 20280 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } - 20280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff60 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20290 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 52 <= 0000000020000400000000001fffff44000000 - 20290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:80 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2029 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 -instret:81 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2030 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 53 <= 0000000020000806000000001fffff44000000 -[ALU redirect - 1] 'h1ffff00000000000000000000800010c6; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } - 20310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:82 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2031 -instret:83 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2031 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:84 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2033 -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff74 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 0000000020000806000000001fffff44000000 - 20400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 20400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h90c8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002be }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000020040833000000001fffff44000000 - 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } - 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90c8 } - 20410 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } } - 20410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102040 -After delta: vaddr = 0x80102040 -instret:85 PC:0x1ffff00000000000000000000800010c6 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2041 -calling cycle -[RFile] wr_ 0: r 56 <= 0000000020040810000000001fffff44000000 - 20420 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 55 <= 0000000020000800000000001fffff44000000 - 20420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080102040 o: 'h0000000080102040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002018 o: 'h0000000080002018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102040 o: 'h0000000080102040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102040, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20430 : [doFinishMem] DTlbResp { resp: <'h0000000080102040,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102040 o: 'h0000000080102040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102040, check_high: 'h00000000080102048, check_inclusive: True } }, specBits: 'h000 } - 20430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -calling cycle -[RFile] wr_ 1: r 4c <= 0000000020000436800000001fffff44000000 - 20440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:86 PC:0x1ffff00000000000000000000800010c8 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2044 -instret:87 PC:0x1ffff00000000000000000000800010cc instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2044 -calling cycle -[RFile] wr_ 0: r 5d <= 0000000020000438800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } - 20450 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 20450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h90d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d6 } -instret:88 PC:0x1ffff00000000000000000000800010d0 instr:0xf7460613 iType:Alu [doCommitNormalInst [0]] 2045 -instret:89 PC:0x1ffff00000000000000000000800010d4 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2045 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102040, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90d4 } - 20460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080102040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d4 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d6 } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d6 } - 20470 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 20470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 20480 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000000000000c00000001fffff44000000 - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080102040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d4 } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080102040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90d4 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:90 PC:0x1ffff00000000000000000000800010d6 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2050 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 0000000000000006000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:91 PC:0x1ffff00000000000000000000800010d8 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2052 -instret:92 PC:0x1ffff00000000000000000000800010da instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2052 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 20530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:93 PC:0x1ffff00000000000000000000800010de instr:0x2be080e7 iType:Jr [doCommitNormalInst [0]] 2053 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 00000000200003d4000000001fffff44000000 - 20540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800010e2 o: 'h00000000800010e2 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 20540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 00000000200003ec000000001fffff44000000 - 20550 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 20550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 19040 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 19040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } +instret:77 PC:0x1ffff0000000000000000000080000448 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 1904 +instret:78 PC:0x1ffff000000000000000000008000044c instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 1904 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19050 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 00000000200003f0000000001fffff44000000 + 19050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } + 19050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 19050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:79 PC:0x1ffff000000000000000000008000044e instr:0xfea43423 iType:St [doCommitNormalInst [0]] 1905 +instret:80 PC:0x1ffff0000000000000000000080000452 instr:0x0040006f iType:J [doCommitNormalInst [1]] 1905 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 19060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f90 After delta: vaddr = 0x80000f90 - 20550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:94 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2055 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 19060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 20560 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 20560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } + 19070 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001000, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 20560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 19070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f90 After delta: vaddr = 0x80000f90 - 20560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:95 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2056 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000001c00000001fffff44000000 - 20570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 20570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 19080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 20570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } + 19080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 19090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 19090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 19090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f90 After delta: vaddr = 0x80000f90 - 20570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -instret:96 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2057 -instret:97 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2057 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 20580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 20580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } + 19100 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000000000000000000001fffff44000000 + 19100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:98 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2058 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 19100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff68 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 20590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 20590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20590 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000006000000001fffff44000000 - 20590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20600 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000006000000001fffff44000000 - 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 20610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 20610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -instret:99 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2061 -instret:100 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2061 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 20620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 3ffffffffffffffa0fff00001fffff44000000 - 20630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } - 20630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } -instret:101 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2063 -instret:102 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2063 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 69 <= 0000000000000000000000001fffff44000000 - 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 20640 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 20640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 20640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:103 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2064 -instret:104 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2064 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 6b <= 0000000000000006000000001fffff44000000 - 20650 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 20650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 20650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:105 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2065 -instret:106 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2065 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 72 <= 0000000020040814000000001fffff44000000 - 20660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } - 20660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 20660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } -instret:107 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2066 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 20670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 20670 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } - 20670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 -instret:108 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2067 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 00000000200003ec000000001fffff44000000 - 20680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 20680 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000020040814000000001fffff44000000 - 20680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:109 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2068 -instret:110 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2068 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 000000002000094d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 20690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 20690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 20690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000020000802000000001fffff44000000 - 20700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 20700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 20700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20710 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 20710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 20710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 20720 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 20720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 20720 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 20720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 20730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 20730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20730 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 20730 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 20730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 20730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20740 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 000000002000080c000000001fffff44000000 - 20740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 20740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20750 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 20750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20750 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 - 20750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 20750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20760 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 20760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 20760 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 20760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 3ffffffffffffbe00fff00001fffff44000000 - 20770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 20770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20770 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000080c000000001fffff44000000 - 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 20770 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 20770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 20770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 3ffffffffffffbd80fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20780 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000080c000000001fffff44000000 - 20780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 20780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 20790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20790 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000008000000001fffff44000000 - 20790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 20790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 20800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 20800 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000008000000001fffff44000000 - 20800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 20810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 20810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000020000814000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20820 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 000000002000080c000000001fffff44000000 - 20820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 20820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20830 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 20830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002030 -After delta: vaddr = 0x80002030 - 20830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 20840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 20840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002030, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 20840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 19110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8182 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 19110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f98 After delta: vaddr = 0x80000f98 - 20840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle - 20860 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 19130 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } calling cycle calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 20920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 20930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + 19550 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } +calling cycle + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h844e } + 19570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h844e } +calling cycle + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h844e } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h844e } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 19580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 19930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 19930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 20940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } + 19940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 20950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 20950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 20950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 20950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 71 <= 00000000200408f7800000001fffff44000000 - 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 20960 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 20960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 20960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 19940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 20960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 19940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 72 <= 0000000020040814000000001fffff44000000 - 20970 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 20970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } + 19950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 19950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8456 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 20970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 19950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 20970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 19950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 20980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 20980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } + 19960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 19960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h845a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 20980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 19960 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } calling cycle - 20990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 20990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 20990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:111 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2099 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[RFile] wr_ 1: r 53 <= 00000000200003d4000000001fffff44000000 + 19970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 19970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h845c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 19970 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 0000000020000402000000001fffff44000000 + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 19970 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 19970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 78 <= 00000000200003ec000000001fffff44000000 - 21000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 21000 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 75 <= 0000000020040814000000001fffff44000000 - 21000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19980 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000020000059000000001fffff44000000 + 19980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 19980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 19980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 19980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 19980 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 19980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 79 <= 000000002000094d000000001fffff44000000 - 21010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 21010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:112 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2101 -instret:113 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2101 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 19990 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 00000000200003f0000000001fffff44000000 + 19990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:81 PC:0x1ffff0000000000000000000080000456 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 1999 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 77 <= 0000000020000802000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 21020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:114 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2102 -instret:115 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2102 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21030 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 21030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -instret:116 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2103 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21040 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 21040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 21040 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 21040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } -instret:117 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2104 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 - 21050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 21050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21050 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000000000000000000001fffff44000000 - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 21050 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 21050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21060 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 000000002000080c000000001fffff44000000 - 21060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 21060 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 21060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21070 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 21070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21070 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 - 21070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:118 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2107 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21080 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 21080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 21080 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 21080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 3ffffffffffffbe00fff00001fffff44000000 - 21090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 21090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21090 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000080c000000001fffff44000000 - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 21090 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 21090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } -instret:119 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2109 -instret:120 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2109 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 3ffffffffffffbd80fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21100 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000080c000000001fffff44000000 - 21100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 21100 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 21100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f80 After delta: vaddr = 0x80000f80 - 21100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:121 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2110 -instret:122 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2110 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:82 PC:0x1ffff000000000000000000008000045a instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 21110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 21110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21110 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000000000008000000001fffff44000000 - 21110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +[ALU redirect - 1] 'h1ffff0000000000000000000080000164; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 20010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 21110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 20010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f80 After delta: vaddr = 0x80000f80 - 21110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:123 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2111 -instret:124 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2111 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 20010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:83 PC:0x1ffff000000000000000000008000045c instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2001 +instret:84 PC:0x1ffff000000000000000000008000045e instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2001 calling cycle - 21120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 21120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 21120 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } } - 21120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:85 PC:0x1ffff0000000000000000000080000460 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2003 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0b6 }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 21120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:125 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2112 -instret:126 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2112 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 20080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 21130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 21130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21130 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000000000008000000001fffff44000000 - 21130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } + 20090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 21130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 20090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:127 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2113 -instret:128 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2113 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 20090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 47 <= 0000000020000814000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 21140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21140 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 02 <= 000000002000080c000000001fffff44000000 - 21140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } + 20100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 20100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 21140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } + 20100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 20110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:86 PC:0x1ffff0000000000000000000080000164 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2011 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff68 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8164 } + 20120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8182 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 20120 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 57 <= 0000000020000402000000001fffff44000000 + 20120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f98 After delta: vaddr = 0x80000f98 - 21140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:129 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2114 -instret:130 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2114 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 20120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21150 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 21150 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 000000002000080c000000001fffff44000000 - 21150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20130 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000020000402000000001fffff44000000 + 20130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 21150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002030 -After delta: vaddr = 0x80002030 - 21150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:131 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2115 -instret:132 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2115 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + 20130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 20130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000100 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle - 21160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 21160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002030, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +[RFile] wr_ 0: r 55 <= 0000000020000063800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 20140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } + 20140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h818a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 20140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 21160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -instret:133 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2116 -instret:134 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2116 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 20140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } +instret:87 PC:0x1ffff0000000000000000000080000168 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2014 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21170 : [doFinishMem] DTlbResp { resp: <'h0000000080002030,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002030 o: 'h0000000080002030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002030, check_high: 'h00000000080002038, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 21170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } +[RFile] wr_ 0: r 5e <= 0000000020000065800000001fffff44000000 +[ALU redirect - 0] 'h1ffff00000000000000000000800000f6; 'h2; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } + 20150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 21170 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 21170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 20150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + 20150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + 20150 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 20150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 20150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ROB incorrectSpec] 'h2 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 20170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 20170 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000007800000001fffff44000000 +instret:88 PC:0x1ffff000000000000000000008000016c instr:0x0000c119 iType:Br [doCommitNormalInst [0]] 2017 +instret:89 PC:0x1ffff000000000000000000008000016e instr:0x0140006f iType:J [doCommitNormalInst [1]] 2017 +calling cycle +instret:90 PC:0x1ffff0000000000000000000080000182 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2018 +instret:91 PC:0x1ffff0000000000000000000080000186 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2018 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8186 } + 20190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8186 } +calling cycle + 20200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8186 } + 20200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8186 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:92 PC:0x1ffff000000000000000000008000018a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2020 +instret:93 PC:0x1ffff000000000000000000008000018e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2020 +calling cycle +instret:94 PC:0x1ffff0000000000000000000080000192 instr:0xf68080e7 iType:Jr [doCommitNormalInst [0]] 2021 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 20740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 20740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5f <= 00000000200003c8000000001fffff44000000 + 20750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000196 o: 'h0000000080000196 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 20750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +calling cycle +[RFile] wr_ 1: r 41 <= 00000000200003d4000000001fffff44000000 + 20760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 20760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:95 PC:0x1ffff00000000000000000000800000f6 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 2076 +calling cycle + 20770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } +instret:96 PC:0x1ffff00000000000000000000800000f8 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 2077 +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80f8 } + 20780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f8 } +instret:97 PC:0x1ffff00000000000000000000800000fa instr:0x0000f022 iType:St [doCommitNormalInst [0]] 2078 +instret:98 PC:0x1ffff00000000000000000000800000fc instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 2078 +calling cycle + 20790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f8 } + 20790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80fa } + 20800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fa } +calling cycle + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fa } + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fa } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 20810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRAM, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 21260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 21270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffef2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 21280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 21280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Xor, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 21290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:99 PC:0x1ffff00000000000000000000800000fe instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2129 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 62 <= 0000000020004443800000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80fe } + 21300 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 0000000000000007800000001fffff44000000 + 21300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 21300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 67 <= 0000000020004400000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + 21310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 21310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21320 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 21320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080011000, shiftedBE: tagged DataMemAccess , pcHash: 'h8116 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 21320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080011000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8116 } +instret:100 PC:0x1ffff0000000000000000000080000102 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2132 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 65 <= 3fffffffffffffffcfff00001fffff44000000 + 21330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 21330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8118 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffffffffffff o: 'hffffffffffffffff b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080011000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8116 } + 21330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080011000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8116 } + 21330 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 21330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 21330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 21340 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 0000000004000000000000001fffff44000000 + 21340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 21340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 21340 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 21340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:101 PC:0x1ffff0000000000000000000080000106 instr:0xfe95055b iType:Cap [doCommitNormalInst [0]] 2134 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 21350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8128 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21350 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000007800000001fffff44000000 + 21350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 21350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } +instret:102 PC:0x1ffff000000000000000000008000010a instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2135 +instret:103 PC:0x1ffff000000000000000000008000010e instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 2135 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080011000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h810a } + 21360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + 21360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + 21360 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 21360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 21360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h810a } +instret:104 PC:0x1ffff0000000000000000000080000112 instr:0xef250593 iType:Alu [doCommitNormalInst [0]] 2136 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 21370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 21370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8134 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21370 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000007800000001fffff44000000 + 21370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h810a } + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h810a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } +instret:105 PC:0x1ffff0000000000000000000080000116 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 2137 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 3ffffffffffffff84fff00001fffff44000000 + 21380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 21380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 21380 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 21380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000003fffff8400000001fffff44000000 + 21390 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000020004404000000001fffff44000000 + 21390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 21390 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 21390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 6e <= 0000000000000007800000001fffff44000000 + 21400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 21400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8140 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21400 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000020000400000000001fffff44000000 + 21400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 21400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 21410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 21410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 21410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 21410 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 21410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 21410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 00000000200003d4000000001fffff44000000 + 21420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 21420 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000020004404000000001fffff44000000 + 21420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 21420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000040004804000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 21430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8144 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000100012010 o: 'h0000000100012010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 21430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 21440 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 21440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 21440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 21440 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 21440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 21450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 21450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21450 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000020000065800000001fffff44000000 + 21450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 21460 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 21460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 40000000000000000000ffff1fffff44000000 + 21470 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 00000000200003f0000000001fffff44000000 + 21470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 21490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 21500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 21510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h819a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 21510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 21510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 21520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h819e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21520 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000020004404000000001fffff44000000 + 21520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 21520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 21520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 21530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 21530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 21530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 21530 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 21530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 21530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 21540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 21540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81b0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 21540 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000020000402000000001fffff44000000 + 21540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 21540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 Before delta: vaddr = 0x80000f98 After delta: vaddr = 0x80000f98 - 21170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -instret:135 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2117 -instret:136 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2117 + 21540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 45 <= 00000000200003ec000000001fffff44000000 -[RFile] wr_ 1: r 08 <= 000000002000080e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21180 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 21180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21180 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000020000806000000001fffff44000000 - 21180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002038 o: 'h0000000080002038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 21550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 21550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h81b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21550 : [doRespLdForward] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7e <= 40000000000000000000ffff1fffff44000000 + 21550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } L1 TLB inc - 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 21550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 21180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -instret:137 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2118 -instret:138 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2118 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 21550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 21190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 21190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } + 21560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 21560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 21560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } L1 TLB inc - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 21190 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 21190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:139 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2119 -instret:140 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2119 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + 21560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 21560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 21560 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 21560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 21560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 21560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21200 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 21200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21200 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000020000438800000001fffff44000000 - 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:141 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2120 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002030, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 21210 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 21210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -instret:142 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2121 -instret:143 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2121 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 21580 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 21580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 21580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 21580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 21580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 21580 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 21580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -[RFile] wr_ 0: r 57 <= 0000000000000000000000001fffff44000000 -[RFile] wr_ 1: r 01 <= 0000000020000806000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 21220 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000400000000001fffff44000000 - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 21590 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Xor, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 22110 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8118 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 22120 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 22120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22130 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 3fffffffffffffffcfff00001fffff44000000 + 22130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 22140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8128 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 22140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + 22150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + 22150 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 22150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 +instret:106 PC:0x1ffff0000000000000000000080000118 instr:0xfe043603 iType:Ld [doCommitNormalInst [0]] 2215 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000000000001fffff44000000 + 22160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 22160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8134 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22160 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 0000000000000007800000001fffff44000000 + 22160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000004000000000000001fffff44000000 + 22170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 22170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 22170 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 22170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } +instret:107 PC:0x1ffff000000000000000000008000011c instr:0xfff64693 iType:Alu [doCommitNormalInst [0]] 2217 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6d <= 0000000004000000000000001fffff44000000 + 22180 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000020004404000000001fffff44000000 + 22180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000010000000 o: 'h0000000010000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 22180 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 22180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:108 PC:0x1ffff0000000000000000000080000120 instr:0x00009536 iType:Alu [doCommitNormalInst [0]] 2218 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6e <= 0000000000000007800000001fffff44000000 + 22190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 22190 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000020000400000000001fffff44000000 + 22190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 22190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:109 PC:0x1ffff0000000000000000000080000122 instr:0x00008d71 iType:Alu [doCommitNormalInst [0]] 2219 +calling cycle + 22200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 22200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:110 PC:0x1ffff0000000000000000000080000124 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2220 +calling cycle +[RFile] wr_ 1: r 69 <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8124 } + 22210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8140 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 22210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8124 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000040004804000000001fffff44000000 + 22220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 22220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8144 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22220 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000004000000000000001fffff44000000 + 22220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000100012010 o: 'h0000000100012010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8124 } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8124 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 22220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } +instret:111 PC:0x1ffff0000000000000000000080000128 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2222 +instret:112 PC:0x1ffff000000000000000000008000012c instr:0xfe85055b iType:Cap [doCommitNormalInst [1]] 2222 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 22230 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 22230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 22230 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:113 PC:0x1ffff0000000000000000000080000130 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2223 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 22240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8130 } + 22240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22240 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000020000065800000001fffff44000000 + 22240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 22250 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22260 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 00000000200003f0000000001fffff44000000 + 22260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } + 22260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000196; 'h0; InstTag { way: 'h0, ptr: 'h08, t: 'h10 } + 22270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h08, t: 'h10 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 22380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 22400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8134 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 22410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 22410 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } } + 22410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 22410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22420 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 72 <= 0000000004000000000000001fffff44000000 + 22420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 22420 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 22420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 22430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8140 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22430 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000007800000001fffff44000000 + 22430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 22430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 22440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8144 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 22440 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 22440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } +instret:114 PC:0x1ffff0000000000000000000080000134 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2244 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 00000000200003d4000000001fffff44000000 + 22450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 22450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22450 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000004000000000000001fffff44000000 + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 22450 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 22450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 22450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } +instret:115 PC:0x1ffff0000000000000000000080000138 instr:0xfd043603 iType:Ld [doCommitNormalInst [0]] 2245 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000da }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 0000000004000007800000001fffff44000000 + 22460 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000020000065800000001fffff44000000 + 22460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000001000001e o: 'h000000001000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 22460 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 22460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 22470 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 22470 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 00000000200003f0000000001fffff44000000 + 22470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:116 PC:0x1ffff000000000000000000008000013c instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 2247 +calling cycle +[RFile] wr_ 1: r 78 <= 0000000000000004000000001fffff44000000 + 22480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 +instret:117 PC:0x1ffff000000000000000000008000013e instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2248 +calling cycle +[RFile] wr_ 1: r 7c <= 000000002000001c800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000196; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080011000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h813e } + 22490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000010000000 o: 'h0000000010000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080011000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h813e } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080011000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h813e } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080011000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h813e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:118 PC:0x1ffff0000000000000000000080000140 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2251 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:119 PC:0x1ffff0000000000000000000080000144 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 2252 +calling cycle +instret:120 PC:0x1ffff0000000000000000000080000146 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 2253 +instret:121 PC:0x1ffff0000000000000000000080000148 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 2253 +calling cycle +instret:122 PC:0x1ffff000000000000000000008000014a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2254 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000010000000 o: 'h0000000010000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 22570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 22590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h819a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 22590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:123 PC:0x1ffff0000000000000000000080000196 instr:0xfca43023 iType:St [doCommitNormalInst [0]] 2259 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8196 } + 22600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h819e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22600 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000004000000000000001fffff44000000 + 22600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 22610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 22610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 22610 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } } + 22610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8196 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22620 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7c <= 0000000020000402000000001fffff44000000 + 22620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8196 } + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8196 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:124 PC:0x1ffff000000000000000000008000019a instr:0xfc043503 iType:Ld [doCommitNormalInst [0]] 2262 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81b0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 22630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 22640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h81b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22640 : [doRespLdForward] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7e <= 40000000000000000000ffff1fffff44000000 + 22640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } +instret:125 PC:0x1ffff000000000000000000008000019e instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2264 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 3fffffffe3fffbfe0fff00001fffff44000000 + 22650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffeff8 o: 'hffffffff8fffeff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 22650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 22650 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 22650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 22650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 22660 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000020000402000000001fffff44000000 + 22660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:126 PC:0x1ffff00000000000000000000800001a2 instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2266 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 22670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 22670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } +instret:127 PC:0x1ffff00000000000000000000800001a4 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 2267 +instret:128 PC:0x1ffff00000000000000000000800001a8 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 2267 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81a4 } + 22680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81cc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 22680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 22680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 22680 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 22680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +instret:129 PC:0x1ffff00000000000000000000800001ac instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2268 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 40000000200004020000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 22690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h81d0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22690 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000007800000001fffff44000000 + 22690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 22690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 22690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81ac } + 22700 : [doRespLdForward] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 02 <= 40000000000000000000ffff1fffff44000000 + 22700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 22700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 22700 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 22700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 22700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ac } +instret:130 PC:0x1ffff00000000000000000000800001b0 instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2270 +calling cycle + 22710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 22710 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000000000000001fffff44000000 + 22710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ac } + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ac } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 22710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 +instret:131 PC:0x1ffff00000000000000000000800001b4 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2271 +instret:132 PC:0x1ffff00000000000000000000800001b8 instr:0x20b5055b iType:Cap [doCommitNormalInst [1]] 2271 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000079000000001fffff44000000 +[RFile] wr_ 1: r 01 <= 0000000000000007800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 22720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22720 : [doRespLdForward] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 45 <= 40000000200004020000ffff1fffff44000000 + 22720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000001e o: 'h000000000000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } +instret:133 PC:0x1ffff00000000000000000000800001bc instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2272 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000da }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 000000002000007b000000001fffff44000000 +[ALU redirect - 0] 'h1ffff0000000000000000000080000208; 'h0; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } + 22730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81bc } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 22730 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +instret:134 PC:0x1ffff00000000000000000000800001c0 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2273 +instret:135 PC:0x1ffff00000000000000000000800001c4 instr:0xfe85055b iType:Cap [doCommitNormalInst [1]] 2273 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h0f, t: 'h1e } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[RFile] wr_ 1: r 0a <= 40000000000000000000ffff1ffff800000000 + 22750 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 3fffffffe3fffbfe0fff00001fffff44000000 + 22750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h00000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 22750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:136 PC:0x1ffff00000000000000000000800001c8 instr:0xf8a43c23 iType:St [doCommitNormalInst [0]] 2275 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 22760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81c8 } + 22760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c8 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 22770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c8 } + 22770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 22770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 22870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81cc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 22890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h81d0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + 22890 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 22890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22900 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 02 <= 40000000200004020000ffff1fffff44000000 + 22900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 22900 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 22910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22910 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000000000007800000001fffff44000000 + 22910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 0000000020000079000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 22920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 22920 : [Ld resp] 'h0a; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 22920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 22920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } +instret:137 PC:0x1ffff00000000000000000000800001cc instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2292 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 000000002000007b000000001fffff44000000 +[RFile] wr_ 1: r 4e <= 00000000200003c4000000001fffff44000000 + 22930 : [doRespLdMem] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 45 <= 40000000200004020000ffff1fffff44000000 + 22930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001ec o: 'h00000000800001ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 22930 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 22930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 22930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:138 PC:0x1ffff00000000000000000000800001d0 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 2293 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0a <= 40000000200004021008ffff1ffff804099008 + 22940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 22940 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 3fffffffe3fffbfe0fff00001fffff44000000 + 22940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 22940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 22940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 00000000200003d4000000001fffff44000000 + 22950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 22950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 22950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:139 PC:0x1ffff00000000000000000000800001d4 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 2295 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 22960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 22960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 22960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:140 PC:0x1ffff00000000000000000000800001d8 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2296 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 22970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81d8 } + 22970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffeff8 o: 'hffffffff8fffeff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 22970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 22970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 22980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 22980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d8 } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 22980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 22980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 22980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 22990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 22990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8218 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 22990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 22990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 22990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 23000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23000 : [doRespLdForward] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 51 <= 40000000200004020000ffff1fffff44000000 + 23000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 23010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23010 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 3fffffffe3fffbfe0fff00001fffff44000000 + 23010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 23010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } +calling cycle +calling cycle + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 23030 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 23030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 23040 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 23100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 23120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000079000000001fffff44000000 + 23130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 23130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 23130 : [Ld resp] 'h0c; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4e <= 00000000200003c4000000001fffff44000000 +[RFile] wr_ 1: r 42 <= 000000002000007b000000001fffff44000000 + 23140 : [doRespLdMem] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 45 <= 40000000200004021008ffff1ffff804099008 + 23140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001ec o: 'h00000000800001ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 23140 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } + 23140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 23140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 23150 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4d <= 3fffffffe3fffbfe0fff00001fffff44000000 + 23150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 23150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5d <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23160 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 23160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001008 o: 'h0000000000000000 b: 'h0000000080001008 t: 'h00000000080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 23160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 23160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:141 PC:0x1ffff00000000000000000000800001dc instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2316 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 23170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffeff8 o: 'hffffffff8fffeff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 23170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:142 PC:0x1ffff00000000000000000000800001e0 instr:0xfb842583 iType:Ld [doCommitNormalInst [0]] 2317 +instret:143 PC:0x1ffff00000000000000000000800001e4 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2317 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 23180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 23180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c +instret:144 PC:0x1ffff00000000000000000000800001e8 instr:0x024080e7 iType:Jr [doCommitNormalInst [0]] 2318 +instret:145 PC:0x1ffff0000000000000000000080000208 instr:0x00007139 iType:Alu [doCommitNormalInst [1]] 2318 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 23190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8218 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 23190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:146 PC:0x1ffff000000000000000000008000020a instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 2319 +instret:147 PC:0x1ffff000000000000000000008000020c instr:0x0000f822 iType:St [doCommitNormalInst [1]] 2319 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h820a } + 23200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23200 : [doRespLdForward] 'h0e; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 51 <= 40000000200004021008ffff1ffff804099008 + 23200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 23200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820a } +instret:148 PC:0x1ffff000000000000000000008000020e instr:0x00000080 iType:Alu [doCommitNormalInst [0]] 2320 +instret:149 PC:0x1ffff0000000000000000000080000210 instr:0xfea44023 iType:St [doCommitNormalInst [1]] 2320 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h2 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23210 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4f <= 3fffffffe3fffbfe0fff00001fffff44000000 + 23210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820a } + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:150 PC:0x1ffff0000000000000000000080000214 instr:0xfcb42e23 iType:St [doCommitNormalInst [0]] 2321 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h820c } + 23220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 23220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } +instret:151 PC:0x1ffff0000000000000000000080000218 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2322 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 23230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h822c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 23230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 23230 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 23230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 23230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } +instret:152 PC:0x1ffff000000000000000000008000021c instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2323 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 00000000200003d4000000001fffff44000000 +[RFile] wr_ 1: r 59 <= 7ffdff00200004021008ffff1ffff804099008 + 23240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 23240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h822e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 23240 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff48000028 + 23240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 23240 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 23240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 23250 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 000000002000007b000000001fffff44000000 + 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:153 PC:0x1ffff0000000000000000000080000220 instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2325 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8210 } + 23260 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 00000000200003f0000000001fffff44000000 + 23260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8210 } +instret:154 PC:0x1ffff0000000000000000000080000224 instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2326 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h1 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 23270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8210 } + 23270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8210 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 23270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8214 } + 23280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'hfd80000000000000 b: 'h0280000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 23280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8214 } +calling cycle +calling cycle + 23300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8214 } + 23300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8214 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 23300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8224 } + 23310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8224 } +calling cycle + 23320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8224 } + 23320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8224 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 23370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 23390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 23390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } +calling cycle + 23400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 23400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h822c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 23400 : [Ld resp] 'h12; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 23400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 00000000200003d4000000001fffff44000000 + 23410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 23410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h822e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23410 : [doRespLdMem] 'h12; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 54 <= 7ffdff00200004021008ffff1ffff804099008 + 23410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 23410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 23410 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 23410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23420 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 000000002000007b000000001fffff44000000 + 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822e } + 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822e } + 23420 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 23420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000018, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23430 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 00000000200003f0000000001fffff44000000 + 23430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:155 PC:0x1ffff0000000000000000000080000228 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2343 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 58 <= 3ffdff00200004020fff00001fffff44000000 +[RFile] wr_ 1: r 61 <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 Before delta: vaddr = 0x00000000 After delta: vaddr = 0x00000000 - 21220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:144 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2122 -instret:145 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2122 + 23440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000018, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:156 PC:0x1ffff000000000000000000008000022c instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2344 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 58 <= 0000000000000000400000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff00000000000000000000800010e2; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 21230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +[RFile] wr_ 0: r 4b <= 0000000000000000400000001fffff44000000 +[ALU redirect - 1] 'h1ffff00000000000000000000800001ec; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 23450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } L1 TLB inc - 21230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 23450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 21230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 21340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 21350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 21360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 21360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 21370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 21370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 21370 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 21370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 1: r 45 <= 00000000200003ec000000001fffff44000000 - 21380 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 21380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21380 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 000000002000080e000000001fffff44000000 - 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 21380 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 21380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21390 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000020000438800000001fffff44000000 - 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 21390 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } - 21390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21400 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 54 <= 0000000020000400000000001fffff44000000 -instret:146 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2140 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:147 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2141 -calling cycle -[ALU redirect - 1] 'h1ffff00000000000000000000800010e2; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:148 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2142 -instret:149 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2142 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:150 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff60 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 000000002000080e000000001fffff44000000 - 21530 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 21530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h90e4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90e4 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000002a2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 000000002004083a000000001fffff44000000 - 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90e4 } - 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90e4 } - 21540 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } } - 21540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102048 -After delta: vaddr = 0x80102048 -instret:151 PC:0x1ffff00000000000000000000800010e2 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2154 -calling cycle -[RFile] wr_ 0: r 55 <= 0000000020040812000000001fffff44000000 - 21550 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 57 <= 0000000020000800000000001fffff44000000 - 21550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080102048 o: 'h0000000080102048 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002038 o: 'h0000000080002038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102048 o: 'h0000000080102048 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102048, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21560 : [doFinishMem] DTlbResp { resp: <'h0000000080102048,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102048 o: 'h0000000080102048 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102048, check_high: 'h00000000080102050, check_inclusive: True } }, specBits: 'h000 } - 21560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -calling cycle -[RFile] wr_ 1: r 50 <= 000000002000043d800000001fffff44000000 - 21570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:152 PC:0x1ffff00000000000000000000800010e4 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2157 -instret:153 PC:0x1ffff00000000000000000000800010e8 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2157 -calling cycle -[RFile] wr_ 0: r 4f <= 000000002000043f800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } - 21580 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 21580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h90f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f2 } -instret:154 PC:0x1ffff00000000000000000000800010ec instr:0xf6060613 iType:Alu [doCommitNormalInst [0]] 2158 -instret:155 PC:0x1ffff00000000000000000000800010f0 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2158 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102048, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h90f0 } - 21590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f0 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f2 } - 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f2 } - 21600 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 21600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 21610 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000000000000c00000001fffff44000000 - 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f0 } - 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h90f0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:156 PC:0x1ffff00000000000000000000800010f2 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2163 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 0000000000000006000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:157 PC:0x1ffff00000000000000000000800010f4 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2165 -instret:158 PC:0x1ffff00000000000000000000800010f6 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2165 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 21660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:159 PC:0x1ffff00000000000000000000800010fa instr:0x2a2080e7 iType:Jr [doCommitNormalInst [0]] 2166 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 00000000200003d4000000001fffff44000000 - 21670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800010fe o: 'h00000000800010fe b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 21670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 53 <= 00000000200003ec000000001fffff44000000 - 21680 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 21680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 21680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:160 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2168 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21690 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 21690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 21690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:161 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2169 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000001c00000001fffff44000000 - 21700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 21700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 21700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -instret:162 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2170 -instret:163 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2170 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 21710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 21710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:164 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2171 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 21720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21720 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000006000000001fffff44000000 - 21720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21730 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000006000000001fffff44000000 - 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 21740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 21740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -instret:165 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2174 -instret:166 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2174 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 3ffffffffffffffa0fff00001fffff44000000 - 21760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } - 21760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } -instret:167 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2176 -instret:168 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2176 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6b <= 0000000000000000000000001fffff44000000 - 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 21770 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 21770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 21770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:169 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2177 -instret:170 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2177 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 6a <= 0000000000000006000000001fffff44000000 - 21780 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 21780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 21780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:171 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2178 -instret:172 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2178 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 73 <= 0000000020040814000000001fffff44000000 - 21790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } - 21790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } -instret:173 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2179 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 21800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 21800 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } } - 21800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 -instret:174 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2180 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 00000000200003ec000000001fffff44000000 - 21810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 21810 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000020040814000000001fffff44000000 - 21810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:175 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2181 -instret:176 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2181 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 000000002000094d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 21820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 21820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 21820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000020000802000000001fffff44000000 - 21830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 21830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21840 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 21840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 21850 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 21850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 21850 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 21850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 21860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 21860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21860 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 21860 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 21860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21870 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000814000000001fffff44000000 - 21870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21880 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 21880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21880 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - 21880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21890 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 21890 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 21890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 21890 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 21890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 21890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 3ffffffffffffbd80fff00001fffff44000000 - 21900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 21900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21900 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000814000000001fffff44000000 - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 21900 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 21900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 21900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 21900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 3ffffffffffffbd00fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21910 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000814000000001fffff44000000 - 21910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 21910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 21920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21920 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000008000000001fffff44000000 - 21920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 21920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 21930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 21930 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000008000000001fffff44000000 - 21930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 21940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 21940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 21940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 000000002000081c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21950 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000020000814000000001fffff44000000 - 21950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 21950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 21960 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 21960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002050 -After delta: vaddr = 0x80002050 - 21960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 21970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 21970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 21970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002050, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 21970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 21970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle - 21990 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 22060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 22070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 22080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 70 <= 00000000200408f7800000001fffff44000000 - 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 22090 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 22090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 22090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 0000000020040814000000001fffff44000000 - 22100 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 22100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 22100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 22110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 22120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 22120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:177 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2212 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 00000000200003ec000000001fffff44000000 - 22130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 22130 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 74 <= 0000000020040814000000001fffff44000000 - 22130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 000000002000094d000000001fffff44000000 - 22140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 22140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:178 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2214 -instret:179 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2214 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 0000000020000802000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 22150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 22150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:180 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2215 -instret:181 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2215 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22160 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 22160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 22160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -instret:182 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2216 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 22170 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 22170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 22170 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 22170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } -instret:183 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2217 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 - 22180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 22180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22180 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000000000000000000001fffff44000000 - 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 22180 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 22180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 22180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22190 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000814000000001fffff44000000 - 22190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 22190 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 22190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 22190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22200 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 22200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22200 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - 22200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 22200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:184 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2220 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22210 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 22210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 22210 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 22210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 3ffffffffffffbd80fff00001fffff44000000 - 22220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 22220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22220 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000814000000001fffff44000000 - 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 22220 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 22220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 22220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } -instret:185 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2222 -instret:186 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2222 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 3ffffffffffffbd00fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22230 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000814000000001fffff44000000 - 22230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 22230 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 22230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 22230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:187 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2223 -instret:188 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2223 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 22240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22240 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000000000008000000001fffff44000000 - 22240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 22240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:189 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2224 -instret:190 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2224 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 22250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 22250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 22250 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } - 22250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 22250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:191 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2225 -instret:192 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2225 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 22260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 22260 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 0000000000000008000000001fffff44000000 - 22260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0c, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 22260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:193 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2226 -instret:194 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2226 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0b <= 000000002000081c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 22270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 22270 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4a <= 0000000020000814000000001fffff44000000 - 22270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 22270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:195 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2227 -instret:196 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2227 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22280 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 22280 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000020000814000000001fffff44000000 - 22280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002050 -After delta: vaddr = 0x80002050 - 22280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:197 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2228 -instret:198 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2228 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 22290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002050, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 22290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -instret:199 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2229 -instret:200 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2229 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22300 : [doFinishMem] DTlbResp { resp: <'h0000000080002050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002050 o: 'h0000000080002050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002050, check_high: 'h00000000080002058, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 22300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 22300 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 22300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 22300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -instret:201 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2230 -instret:202 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2230 -calling cycle -[RFile] wr_ 0: r 02 <= 00000000200003ec000000001fffff44000000 -[RFile] wr_ 1: r 5b <= 0000000020000816000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22310 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 22310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22310 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 000000002000080e000000001fffff44000000 - 22310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002058 o: 'h0000000080002058 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 22310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -instret:203 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2231 -instret:204 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2231 -calling cycle - 22320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 22320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 22320 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 22320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:205 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2232 -instret:206 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2232 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22330 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 22330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22330 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 000000002000043f800000001fffff44000000 - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:207 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2233 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002050, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 22340 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 22340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -instret:208 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2234 -instret:209 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2234 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 22350 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000020000400000000001fffff44000000 - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 22350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -instret:210 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2235 -instret:211 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2235 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff00000000000000000000800010fe; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } -calling cycle - 22370 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002050, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } - 22370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 22380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 22380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -calling cycle -calling cycle - 22400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002090, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 22400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 22420 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800020d0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 22470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 22480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 22490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 22490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 -calling cycle - 22500 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 22500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22500 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000020000816000000001fffff44000000 - 22500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 1: r 02 <= 00000000200003ec000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 22510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 22510 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 22510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -calling cycle - 22520 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 000000002000043f800000001fffff44000000 - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 22520 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } } - 22520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:212 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2252 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22530 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 42 <= 0000000020000400000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:213 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2254 -calling cycle -[ALU redirect - 1] 'h1ffff00000000000000000000800010fe; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:214 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2255 -instret:215 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2255 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:216 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff2c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 22640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h42, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 22650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 0000000020000816000000001fffff44000000 - 22660 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 22660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h9100 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 22660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9100 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000286 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4b <= 0000000020040841000000001fffff44000000 - 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9100 } - 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9100 } - 22670 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } - 22670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 22670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102030 -After delta: vaddr = 0x80102030 -instret:217 PC:0x1ffff00000000000000000000800010fe instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2267 -calling cycle -[RFile] wr_ 0: r 57 <= 000000002004080c000000001fffff44000000 - 22680 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 58 <= 0000000020000800000000001fffff44000000 - 22680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080102030 o: 'h0000000080102030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002058 o: 'h0000000080002058 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102030 o: 'h0000000080102030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102030, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 22680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 22690 : [doFinishMem] DTlbResp { resp: <'h0000000080102030,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102030 o: 'h0000000080102030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102030, check_high: 'h00000000080102038, check_inclusive: True } }, specBits: 'h000 } - 22690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -calling cycle -[RFile] wr_ 1: r 45 <= 0000000020000444800000001fffff44000000 - 22700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:218 PC:0x1ffff0000000000000000000080001100 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2270 -instret:219 PC:0x1ffff0000000000000000000080001104 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2270 -calling cycle -[RFile] wr_ 0: r 52 <= 0000000020000446800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } - 22710 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 22710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h910e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 22710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910e } -instret:220 PC:0x1ffff0000000000000000000080001108 instr:0xf2c60613 iType:Alu [doCommitNormalInst [0]] 2271 -instret:221 PC:0x1ffff000000000000000000008000110c instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2271 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910e } - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910e } - 22730 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 22730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 22740 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000000000000c00000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:222 PC:0x1ffff000000000000000000008000110e instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2276 -calling cycle -[RFile] wr_ 1: r 50 <= 0000000000000006000000001fffff44000000 -calling cycle -instret:223 PC:0x1ffff0000000000000000000080001110 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2278 -instret:224 PC:0x1ffff0000000000000000000080001112 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2278 -calling cycle -instret:225 PC:0x1ffff0000000000000000000080001116 instr:0x286080e7 iType:Jr [doCommitNormalInst [0]] 2279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 22850 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002050, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } -calling cycle - 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 22870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -calling cycle - 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 22880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102030, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h910c } - 22890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } -calling cycle - 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } - 22900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 22920 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080102030, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 23160 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002090, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 23470 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800020d0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800020d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 23480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 23860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 59 <= 00000000200003d4000000001fffff44000000 - 23870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000111a o: 'h000000008000111a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 23870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 01 <= 00000000200003ec000000001fffff44000000 - 23880 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 23880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 23880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:226 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2388 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 23890 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 23890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 23890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:227 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2389 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 63 <= 0000000000000001c00000001fffff44000000 - 23900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 23900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 -instret:228 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2390 -instret:229 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2390 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 23910 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 23910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:230 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2391 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23920 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } - 23920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 23920 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 64 <= 0000000000000006000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23930 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000006000000001fffff44000000 - 23930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 23940 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 -instret:231 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2394 -instret:232 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2394 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 23950 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 3ffffffffffffffa0fff00001fffff44000000 - 23960 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } - 23960 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } -instret:233 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2396 -instret:234 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2396 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h0aa, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6a <= 0000000000000000000000001fffff44000000 - 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 23970 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 23970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 23970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 23970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:235 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2397 -instret:236 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2397 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 6c <= 0000000000000006000000001fffff44000000 - 23980 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 23980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 23980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:237 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2398 -instret:238 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2398 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 75 <= 0000000020040814000000001fffff44000000 - 23990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } - 23990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 23990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 23990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 23990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 23990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } -instret:239 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2399 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 24000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 24000 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } - 24000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 -instret:240 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2400 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 00000000200003ec000000001fffff44000000 - 24010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 24010 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000020040814000000001fffff44000000 - 24010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:241 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2401 -instret:242 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2401 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 000000002000094d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 24020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 24020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 24020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000020000802000000001fffff44000000 - 24030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24040 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 24040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 24040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 24050 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 24050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0d, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 24050 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 24050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 24060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 24060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24060 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 - 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 24060 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 24060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24070 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 000000002000081c000000001fffff44000000 - 24070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24080 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 24080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24080 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 - 24080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 24080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080102030, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24090 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 24090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 24090 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 3ffffffffffffbd00fff00001fffff44000000 - 24100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 24100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24100 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000081c000000001fffff44000000 - 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h910c } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 3ffffffffffffbc80fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 24110 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000008000000001fffff44000000 - 24110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 24110 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 24110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 24120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24120 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000081c000000001fffff44000000 - 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 24120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 24130 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000008000000001fffff44000000 - 24130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 24130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 24140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000020000824000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 24150 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24150 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000081c000000001fffff44000000 - 24150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 24150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24160 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 24160 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 000000002000081c000000001fffff44000000 - 24160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002070 -After delta: vaddr = 0x80002070 - 24160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 24170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002070, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 24170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 24180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -calling cycle - 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 24190 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 24200 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } - 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h72, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 24280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 72 <= 00000000200408f7800000001fffff44000000 - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 24290 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 24290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 24290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 0000000020040814000000001fffff44000000 - 24300 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 24300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 24310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 24320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:243 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2432 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 00000000200003ec000000001fffff44000000 - 24330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 24330 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 76 <= 0000000020040814000000001fffff44000000 - 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h00a, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 000000002000094d000000001fffff44000000 - 24340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 24340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:244 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2434 -instret:245 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2434 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 0000000020000802000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 24350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:246 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2435 -instret:247 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2435 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24360 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 24360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 24360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -instret:248 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2436 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24370 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 24370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 24370 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } -instret:249 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2437 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 - 24380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 24380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24380 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000000000000000000001fffff44000000 - 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 24380 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24390 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 000000002000081c000000001fffff44000000 - 24390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 24390 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 24390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24400 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 24400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24400 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 - 24400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 24400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:250 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2440 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24410 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 24410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 24410 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 3ffffffffffffbd00fff00001fffff44000000 - 24420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 24420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24420 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000081c000000001fffff44000000 - 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 24420 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 24420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } -instret:251 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2442 -instret:252 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2442 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 3ffffffffffffbc80fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24430 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000081c000000001fffff44000000 - 24430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 24430 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } - 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 24430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:253 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2443 -instret:254 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2443 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 24440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24440 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 47 <= 0000000000000008000000001fffff44000000 - 24440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 24440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:255 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2444 -instret:256 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2444 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 24450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 24450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 24450 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 24450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:257 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2445 -instret:258 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2445 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 24460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24460 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000008000000001fffff44000000 - 24460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 24460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:259 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2446 -instret:260 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2446 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 40 <= 0000000020000824000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 24470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 24470 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 49 <= 000000002000081c000000001fffff44000000 - 24470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 24470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:261 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2447 -instret:262 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2447 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24480 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 24480 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 000000002000081c000000001fffff44000000 - 24480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002070 -After delta: vaddr = 0x80002070 - 24480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:263 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2448 -instret:264 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2448 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 24490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002070, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 24490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -instret:265 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2449 -instret:266 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2449 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24500 : [doFinishMem] DTlbResp { resp: <'h0000000080002070,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002070 o: 'h0000000080002070 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002070, check_high: 'h00000000080002078, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 24500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 24500 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 24500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 24500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -instret:267 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2450 -instret:268 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2450 -calling cycle -[RFile] wr_ 0: r 4a <= 00000000200003ec000000001fffff44000000 -[RFile] wr_ 1: r 5d <= 000000002000081e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24510 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 24510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24510 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000020000816000000001fffff44000000 - 24510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002078 o: 'h0000000080002078 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 24510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -instret:269 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2451 -instret:270 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2451 -calling cycle - 24520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 24520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 24520 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 24520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:271 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2452 -instret:272 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2452 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24530 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 24530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24530 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000020000446800000001fffff44000000 - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:273 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2453 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002070, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 24540 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 24540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -instret:274 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2454 -instret:275 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2454 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 24550 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000020000400000000001fffff44000000 - 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:276 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2455 -instret:277 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2455 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000111a; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 24560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 24670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 24680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 24690 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 24690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 24700 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 24700 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 24700 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 24700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 1: r 4a <= 00000000200003ec000000001fffff44000000 - 24710 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 24710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24710 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 000000002000081e000000001fffff44000000 - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 24710 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24720 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000020000446800000001fffff44000000 - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 24720 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } } - 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24730 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5f <= 0000000020000400000000001fffff44000000 -instret:278 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2473 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:279 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2474 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000111a; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:280 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2475 -instret:281 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2475 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:282 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff18 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 24850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 000000002000081e000000001fffff44000000 - 24860 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 24860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h911c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 24860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h911c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000026a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 51 <= 0000000020040848000000001fffff44000000 - 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h911c } - 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h911c } - 24870 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } - 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 24870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102038 -After delta: vaddr = 0x80102038 -instret:283 PC:0x1ffff000000000000000000008000111a instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2487 -calling cycle -[RFile] wr_ 0: r 58 <= 000000002004080e000000001fffff44000000 - 24880 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4b <= 0000000020000800000000001fffff44000000 - 24880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080102038 o: 'h0000000080102038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002078 o: 'h0000000080002078 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102038 o: 'h0000000080102038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102038, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 24880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 24890 : [doFinishMem] DTlbResp { resp: <'h0000000080102038,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102038 o: 'h0000000080102038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102038, check_high: 'h00000000080102040, check_inclusive: True } }, specBits: 'h000 } - 24890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -calling cycle -[RFile] wr_ 1: r 02 <= 000000002000044b800000001fffff44000000 - 24900 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:284 PC:0x1ffff000000000000000000008000111c instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2490 -instret:285 PC:0x1ffff0000000000000000000080001120 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2490 -calling cycle -[RFile] wr_ 0: r 54 <= 000000002000044d800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } - 24910 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 24910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h912a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 24910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h912a } -instret:286 PC:0x1ffff0000000000000000000080001124 instr:0xf1860613 iType:Alu [doCommitNormalInst [0]] 2491 -instret:287 PC:0x1ffff0000000000000000000080001128 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2491 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102038, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9128 } - 24920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9128 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h912a } - 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h912a } - 24930 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 24940 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000c00000001fffff44000000 - 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9128 } - 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080102038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9128 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 24940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:288 PC:0x1ffff000000000000000000008000112a instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2496 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000000000006000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:289 PC:0x1ffff000000000000000000008000112c instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2498 -instret:290 PC:0x1ffff000000000000000000008000112e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2498 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 24990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 24990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:291 PC:0x1ffff0000000000000000000080001132 instr:0x26a080e7 iType:Jr [doCommitNormalInst [0]] 2499 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5a <= 00000000200003d4000000001fffff44000000 - 25000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001136 o: 'h0000000080001136 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 25000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 46 <= 00000000200003ec000000001fffff44000000 - 25010 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 25010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 25010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:292 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2501 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25020 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 25020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 25020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:293 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2502 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 62 <= 0000000000000001c00000001fffff44000000 - 25030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 25030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 25030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -instret:294 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2503 -instret:295 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2503 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 25040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 25040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:296 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2504 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 25050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25050 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000006000000001fffff44000000 - 25050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 67 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25060 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 66 <= 0000000000000006000000001fffff44000000 - 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 25070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 25070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -instret:297 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2507 -instret:298 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2507 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 65 <= 3ffffffffffffffa0fff00001fffff44000000 - 25090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } - 25090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } -instret:299 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2509 -instret:300 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2509 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h055, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6c <= 0000000000000000000000001fffff44000000 - 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 25100 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 25100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 25100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:301 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2510 -instret:302 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2510 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 73 <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 6e <= 0000000000000006000000001fffff44000000 - 25110 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 25110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 25110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:303 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2511 -instret:304 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2511 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 71 <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 74 <= 0000000020040814000000001fffff44000000 - 25120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } - 25120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } -instret:305 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2512 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 25130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 25130 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } - 25130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 -instret:306 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2513 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 00000000200003ec000000001fffff44000000 - 25140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 25140 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000020040814000000001fffff44000000 - 25140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:307 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2514 -instret:308 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2514 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h005, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 000000002000094d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 25150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 25150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 25150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 0000000020000802000000001fffff44000000 - 25160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25170 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 25170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 25180 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 25180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 25180 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 25180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 25190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 25190 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25190 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 - 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 25190 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 25190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25200 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000824000000001fffff44000000 - 25200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25210 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 25210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25210 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - 25210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25220 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 25220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 25220 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 3ffffffffffffbc80fff00001fffff44000000 - 25230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 25230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25230 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000824000000001fffff44000000 - 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 25230 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 3ffffffffffffbc00fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25240 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000824000000001fffff44000000 - 25240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 25250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25250 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000008000000001fffff44000000 - 25250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 25260 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000008000000001fffff44000000 - 25260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 25270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0c <= 000000002000082c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25280 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000020000824000000001fffff44000000 - 25280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25290 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 25290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002090 -After delta: vaddr = 0x80002090 - 25290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 25300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002090, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 25300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle - 25320 : [doRespLdForward] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 25410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 73 <= 00000000200408f7800000001fffff44000000 - 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 25420 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 25420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 25420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 74 <= 0000000020040814000000001fffff44000000 - 25430 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 25430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 25430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 25440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 25450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:309 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2545 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 00000000200003ec000000001fffff44000000 - 25460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 25460 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 68 <= 0000000020040814000000001fffff44000000 - 25460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h002, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 000000002000094d000000001fffff44000000 - 25470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 25470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:310 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2547 -instret:311 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2547 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 0000000020000802000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 25480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:312 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2548 -instret:313 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2548 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25490 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 25490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -instret:314 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2549 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25500 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 25500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 25500 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 25500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } -instret:315 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2550 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 - 25510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 25510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25510 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000000000000000000001fffff44000000 - 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 25510 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 25510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 55 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25520 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000824000000001fffff44000000 - 25520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 25520 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25530 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 25530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25530 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - 25530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:316 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2553 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25540 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 25540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 25540 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7b <= 3ffffffffffffbc80fff00001fffff44000000 - 25550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 25550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25550 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000824000000001fffff44000000 - 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 25550 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 25550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } -instret:317 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2555 -instret:318 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2555 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7c <= 3ffffffffffffbc00fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25560 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000824000000001fffff44000000 - 25560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 25560 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } - 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:319 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2556 -instret:320 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2556 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 25570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25570 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0b <= 0000000000000008000000001fffff44000000 - 25570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:321 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2557 -instret:322 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2557 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 25580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 25580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 25580 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } } - 25580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 25580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:323 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2558 -instret:324 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2558 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 25590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25590 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 0000000000000008000000001fffff44000000 - 25590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 25590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:325 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2559 -instret:326 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2559 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 0c <= 000000002000082c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 25600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 25600 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000020000824000000001fffff44000000 - 25600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 25600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:327 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2560 -instret:328 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2560 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25610 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 25610 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000020000824000000001fffff44000000 - 25610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002090 -After delta: vaddr = 0x80002090 - 25610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:329 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2561 -instret:330 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2561 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 25620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002090, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 25620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -instret:331 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2562 -instret:332 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2562 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25630 : [doFinishMem] DTlbResp { resp: <'h0000000080002090,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002090 o: 'h0000000080002090 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002090, check_high: 'h00000000080002098, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 25630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 25630 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 25630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 25630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -instret:333 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2563 -instret:334 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2563 -calling cycle -[RFile] wr_ 0: r 49 <= 00000000200003ec000000001fffff44000000 -[RFile] wr_ 1: r 4f <= 0000000020000826000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 25640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25640 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 000000002000081e000000001fffff44000000 - 25640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002098 o: 'h0000000080002098 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 25640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -instret:335 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2564 -instret:336 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2564 -calling cycle - 25650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 25650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 25650 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 25650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:337 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2565 -instret:338 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2565 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25660 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 25660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25660 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 000000002000044d800000001fffff44000000 - 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:339 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2566 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002090, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 25670 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 25670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -instret:340 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2567 -instret:341 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2567 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 25680 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000020000400000000001fffff44000000 - 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:342 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2568 -instret:343 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2568 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff0000000000000000000080001136; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 25690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -calling cycle - 25700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle - 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace -calling cycle -calling cycle - 25750 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002110, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 25800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 25810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 25820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 25820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 25830 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 25830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 25830 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 1: r 49 <= 00000000200003ec000000001fffff44000000 - 25840 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 25840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25840 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000020000826000000001fffff44000000 - 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 25840 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 25840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25850 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 000000002000044d800000001fffff44000000 - 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 25850 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } } - 25850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 25860 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 41 <= 0000000020000400000000001fffff44000000 -instret:344 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2586 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:345 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2587 -calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080001136; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:346 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2588 -instret:347 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2588 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:348 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffedc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 25970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 25980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 0000000020000826000000001fffff44000000 - 25990 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 25990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h9138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 25990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 25990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9138 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h0e, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000024e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5c <= 000000002004084f000000001fffff44000000 - 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9138 } - 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9138 } - 26000 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } - 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102018 -After delta: vaddr = 0x80102018 -instret:349 PC:0x1ffff0000000000000000000080001136 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2600 -calling cycle -[RFile] wr_ 0: r 4b <= 0000000020040806000000001fffff44000000 - 26010 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 51 <= 0000000020000800000000001fffff44000000 - 26010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080102018 o: 'h0000000080102018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080002098 o: 'h0000000080002098 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102018 o: 'h0000000080102018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102018, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26020 : [doFinishMem] DTlbResp { resp: <'h0000000080102018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102018 o: 'h0000000080102018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102018, check_high: 'h00000000080102020, check_inclusive: True } }, specBits: 'h000 } - 26020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -calling cycle -[RFile] wr_ 1: r 4a <= 0000000020000452800000001fffff44000000 - 26030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:350 PC:0x1ffff0000000000000000000080001138 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2603 -instret:351 PC:0x1ffff000000000000000000008000113c instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2603 -calling cycle -[RFile] wr_ 0: r 42 <= 0000000020000454800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } - 26040 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 26040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9146 } -instret:352 PC:0x1ffff0000000000000000000080001140 instr:0xedc60613 iType:Alu [doCommitNormalInst [0]] 2604 -instret:353 PC:0x1ffff0000000000000000000080001144 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2604 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102018, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9144 } - 26050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080102018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9144 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9146 } - 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9146 } - 26060 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } - 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 26070 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 60 <= 0000000000000000c00000001fffff44000000 - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080102018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9144 } - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080102018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9144 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:354 PC:0x1ffff0000000000000000000080001146 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2609 -calling cycle -[RFile] wr_ 1: r 02 <= 0000000000000006000000001fffff44000000 -calling cycle -instret:355 PC:0x1ffff0000000000000000000080001148 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2611 -instret:356 PC:0x1ffff000000000000000000008000114a instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2611 -calling cycle -instret:357 PC:0x1ffff000000000000000000008000114e instr:0x24e080e7 iType:Jr [doCommitNormalInst [0]] 2612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 26230 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002110, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 26620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4c <= 00000000200003d4000000001fffff44000000 - 26630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001152 o: 'h0000000080001152 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 26630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 43 <= 00000000200003ec000000001fffff44000000 - 26640 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 26640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 26640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:358 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2664 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26650 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 26650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 26650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:359 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2665 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 64 <= 0000000000000001c00000001fffff44000000 - 26660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 26660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 26660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -instret:360 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2666 -instret:361 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2666 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 26670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 26670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:362 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2667 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 26680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 26680 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26680 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000000000006000000001fffff44000000 - 26680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 65 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26690 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 67 <= 0000000000000006000000001fffff44000000 - 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 26700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 26700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -instret:363 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2670 -instret:364 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2670 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 26710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 66 <= 3ffffffffffffffa0fff00001fffff44000000 - 26720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } - 26720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } -instret:365 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2672 -instret:366 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2672 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h02a, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6e <= 0000000000000000000000001fffff44000000 - 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 26730 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 26730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:367 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2673 -instret:368 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2673 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 75 <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 6f <= 0000000000000006000000001fffff44000000 - 26740 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 26740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 26740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:369 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2674 -instret:370 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2674 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 70 <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 76 <= 0000000020040814000000001fffff44000000 - 26750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } - 26750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 26750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } -instret:371 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2675 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 26760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 26760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 26760 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } } - 26760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 -instret:372 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2676 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 00000000200003ec000000001fffff44000000 - 26770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 26770 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000020040814000000001fffff44000000 - 26770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:373 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2677 -instret:374 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2677 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h001, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 000000002000094d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 26780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 26780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 26780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 78 <= 0000000020000802000000001fffff44000000 - 26790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 26790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 26790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 26800 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 26800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 26800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 26810 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 26810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 26810 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 26810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 26820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 26820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26820 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 - 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 26820 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 26820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 57 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26830 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 000000002000082c000000001fffff44000000 - 26830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 26830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26840 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 26840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26840 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 - 26840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 26840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26850 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 26850 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 26850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 26850 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 26850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 26850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7a <= 3ffffffffffffbc00fff00001fffff44000000 - 26860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 26860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26860 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000082c000000001fffff44000000 - 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 26860 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 26860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 26860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7e <= 3ffffffffffffbb80fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26870 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000082c000000001fffff44000000 - 26870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 26870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 26880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26880 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000008000000001fffff44000000 - 26880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 26880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 26890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 26890 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000008000000001fffff44000000 - 26890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 26900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 26900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 26900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 56 <= 0000000020000834000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26910 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 000000002000082c000000001fffff44000000 - 26910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 26910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 26920 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 26920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800020b0 -After delta: vaddr = 0x800020b0 - 26920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 26930 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 26930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 26930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 26930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 26930 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle - 26950 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 27040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 75 <= 00000000200408f7800000001fffff44000000 - 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 27050 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 27050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 76 <= 0000000020040814000000001fffff44000000 - 27060 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 27060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 27060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 27070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Valid 'h7b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 27080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 27080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 27080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:375 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2708 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 79 <= 00000000200003ec000000001fffff44000000 - 27090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 27090 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 69 <= 0000000020040814000000001fffff44000000 - 27090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h000, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 000000002000094d000000001fffff44000000 - 27100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 27100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:376 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2710 -instret:377 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2710 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 0000000020000802000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 27110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:378 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2711 -instret:379 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2711 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27120 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 27120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } -instret:380 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2712 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27130 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 27130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 27130 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } } - 27130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } -instret:381 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2713 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 05 <= 0000000020000957000000001fffff44000000 - 27140 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 27140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27140 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6a <= 0000000000000000000000001fffff44000000 - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 27140 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } - 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 57 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27150 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7b <= 000000002000082c000000001fffff44000000 - 27150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 27150 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } - 27150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27160 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 27160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27160 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7f <= 0000000000000008000000001fffff44000000 - 27160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:382 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2716 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27170 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 27170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 27170 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 27170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7a <= 3ffffffffffffbc00fff00001fffff44000000 - 27180 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 27180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27180 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 000000002000082c000000001fffff44000000 - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 27180 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } -instret:383 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2718 -instret:384 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2718 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 7e <= 3ffffffffffffbb80fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27190 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 000000002000082c000000001fffff44000000 - 27190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 27190 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } } - 27190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 27190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:385 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2719 -instret:386 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2719 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 27200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27200 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 40 <= 0000000000000008000000001fffff44000000 - 27200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 27200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:387 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2720 -instret:388 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2720 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 27210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 27210 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } } - 27210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 27210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:389 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2721 -instret:390 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2721 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 27220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 27220 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000000000008000000001fffff44000000 - 27220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:391 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2722 -instret:392 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2722 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 56 <= 0000000020000834000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 27230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 27230 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4d <= 000000002000082c000000001fffff44000000 - 27230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 27230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:393 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2723 -instret:394 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2723 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27240 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 27240 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5d <= 000000002000082c000000001fffff44000000 - 27240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800020b0 -After delta: vaddr = 0x800020b0 - 27240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:395 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2724 -instret:396 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2724 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 27250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 27250 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020b0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 27250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -instret:397 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2725 -instret:398 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2725 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27260 : [doFinishMem] DTlbResp { resp: <'h00000000800020b0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800020b0 o: 'h00000000800020b0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800020b0, check_high: 'h000000000800020b8, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 27260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 27260 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 27260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 27260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -instret:399 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2726 -instret:400 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2726 -calling cycle -[RFile] wr_ 0: r 4e <= 00000000200003ec000000001fffff44000000 -[RFile] wr_ 1: r 52 <= 000000002000082e000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27270 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 27270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27270 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 0000000020000826000000001fffff44000000 - 27270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b8 o: 'h00000000800020b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 27270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -instret:401 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2727 -instret:402 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2727 -calling cycle - 27280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 27280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 27280 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:403 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2728 -instret:404 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2728 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27290 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 27290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27290 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000020000454800000001fffff44000000 - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:405 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2729 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800020b0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 27300 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -instret:406 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2730 -instret:407 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2730 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 27310 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000020000400000000001fffff44000000 - 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:408 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2731 -instret:409 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2731 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff0000000000000000000080001152; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 27320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 27430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 27440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 27450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 27450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 27450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 27460 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 27460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 27460 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } - 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -calling cycle -[RFile] wr_ 1: r 4e <= 00000000200003ec000000001fffff44000000 - 27470 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 27470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27470 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 46 <= 000000002000082e000000001fffff44000000 - 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 27470 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } } - 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27480 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5a <= 0000000020000454800000001fffff44000000 - 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 27480 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 27480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27490 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000020000400000000001fffff44000000 -instret:410 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2749 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:411 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2750 -calling cycle -[ALU redirect - 1] 'h1ffff0000000000000000000080001152; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } -instret:412 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2751 -instret:413 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2751 -calling cycle -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; -calling cycle -instret:414 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffed0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fb8 -After delta: vaddr = 0x80000fb8 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 27610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 0b <= 000000002000082e000000001fffff44000000 - 27620 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } - 27620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h9154 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9154 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h12, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000232 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 5e <= 0000000020040856000000001fffff44000000 - 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9154 } - 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9154 } - 27630 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } } - 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102028 -After delta: vaddr = 0x80102028 -instret:415 PC:0x1ffff0000000000000000000080001152 instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2763 -calling cycle -[RFile] wr_ 0: r 51 <= 000000002004080a000000001fffff44000000 - 27640 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5c <= 0000000020000800000000001fffff44000000 - 27640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080102028 o: 'h0000000080102028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020b8 o: 'h00000000800020b8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102028 o: 'h0000000080102028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102028, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27650 : [doFinishMem] DTlbResp { resp: <'h0000000080102028,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102028 o: 'h0000000080102028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102028, check_high: 'h00000000080102030, check_inclusive: True } }, specBits: 'h000 } - 27650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 -calling cycle -[RFile] wr_ 1: r 49 <= 0000000020000459800000001fffff44000000 - 27660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:416 PC:0x1ffff0000000000000000000080001154 instr:0xfb843503 iType:Ld [doCommitNormalInst [0]] 2766 -instret:417 PC:0x1ffff0000000000000000000080001158 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2766 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h000000b8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5f <= 000000002000045b800000001fffff44000000 -[ALU redirect - 0] 'h1ffff0000000000000000000080001398; 'h0; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } - 27670 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 27670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9162 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h000000b8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h0c, rn2 'h09, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h09, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9162 } -instret:418 PC:0x1ffff000000000000000000008000115c instr:0xed060613 iType:Alu [doCommitNormalInst [0]] 2767 -instret:419 PC:0x1ffff0000000000000000000080001160 instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2767 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102028, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9160 } - 27680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9160 } -[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h06, t: 'h0d } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9162 } - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9162 } - 27690 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } - 27690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 27700 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 59 <= 0000000000000000c00000001fffff44000000 - 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9160 } - 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080102028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9160 } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -instret:420 PC:0x1ffff0000000000000000000080001162 instr:0x00004108 iType:Ld [doCommitNormalInst [0]] 2772 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000006000000001fffff44000000 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:421 PC:0x1ffff0000000000000000000080001164 instr:0x0000050e iType:Alu [doCommitNormalInst [0]] 2774 -instret:422 PC:0x1ffff0000000000000000000080001166 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2774 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 27750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:423 PC:0x1ffff000000000000000000008000116a instr:0x232080e7 iType:Jr [doCommitNormalInst [0]] 2775 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 50 <= 00000000200003d4000000001fffff44000000 - 27760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000116e o: 'h000000008000116e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 27760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h00a, globalTaken: False, localTaken: False, pcIndex: 'h1d6 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 47 <= 00000000200003ec000000001fffff44000000 - 27770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 27770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 27770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:424 PC:0x1ffff0000000000000000000080001398 instr:0x0000711d iType:Alu [doCommitNormalInst [0]] 2777 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27780 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 27780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 27780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:425 PC:0x1ffff000000000000000000008000139a instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2778 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 61 <= 0000000000000001c00000001fffff44000000 - 27790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939a } - 27790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f90 -After delta: vaddr = 0x80000f90 - 27790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -instret:426 PC:0x1ffff000000000000000000008000139c instr:0x0000e8a2 iType:St [doCommitNormalInst [0]] 2779 -instret:427 PC:0x1ffff000000000000000000008000139e instr:0x00001080 iType:Alu [doCommitNormalInst [1]] 2779 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 27800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } - 27800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 27800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } - 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939a } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:428 PC:0x1ffff00000000000000000000800013a0 instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2780 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h939c } - 27810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h93c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 27810 : [doRespLdForward] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 62 <= 0000000000000006000000001fffff44000000 - 27810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 66 <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27820 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 65 <= 0000000000000006000000001fffff44000000 - 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } - 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h939c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93a0 } - 27830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 27830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -instret:429 PC:0x1ffff00000000000000000000800013a4 instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2783 -instret:430 PC:0x1ffff00000000000000000000800013a8 instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2783 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc72 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93a0 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 67 <= 3ffffffffffffffa0fff00001fffff44000000 - 27850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h004 } - 27850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:431 PC:0x1ffff00000000000000000000800013aa instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2785 -instret:432 PC:0x1ffff00000000000000000000800013ae instr:0x0120006f iType:J [doCommitNormalInst [1]] 2785 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h015, globalTaken: False, localTaken: False, pcIndex: 'h1fb }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 6f <= 0000000000000000000000001fffff44000000 - 27860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 27860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:433 PC:0x1ffff00000000000000000000800013c0 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2786 -instret:434 PC:0x1ffff00000000000000000000800013c4 instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2786 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 74 <= 00000000200408f7800000001fffff44000000 -[RFile] wr_ 1: r 71 <= 0000000000000006000000001fffff44000000 - 27870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f58 -After delta: vaddr = 0x80000f58 - 27870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:435 PC:0x1ffff00000000000000000000800013c6 instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2787 -instret:436 PC:0x1ffff00000000000000000000800013c8 instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2787 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 72 <= 0000000000000008000000001fffff44000000 -[RFile] wr_ 1: r 68 <= 0000000020040814000000001fffff44000000 - 27880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h002 } - 27880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - 27880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } -instret:437 PC:0x1ffff00000000000000000000800013ca instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2788 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 27890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } - 27890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 27890 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 27890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:438 PC:0x1ffff00000000000000000000800013cc instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2789 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 77 <= 00000000200003ec000000001fffff44000000 - 27900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 27900 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000020040814000000001fffff44000000 - 27900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:439 PC:0x1ffff00000000000000000000800013ce instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2790 -instret:440 PC:0x1ffff00000000000000000000800013d2 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2790 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h000, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 000000002000094d000000001fffff44000000 -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93ce } - 27910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 27910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000020000802000000001fffff44000000 - 27920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ce } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 27930 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 27930 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h93d6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27940 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 27940 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93d6 } - 27940 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } } - 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 27950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 27950 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27950 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6d <= 0000000000000008000000001fffff44000000 - 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 27950 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 27960 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27960 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 - 27960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 27960 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 27960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 27970 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 27970 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27970 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000834000000001fffff44000000 - 27970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 27970 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 27970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:441 PC:0x1ffff00000000000000000000800013d6 instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2797 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } - 27980 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - 27980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 27980 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 27980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 27980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 27990 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h003 } - 27990 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 27990 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000834000000001fffff44000000 - 27990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 27990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 27990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 27990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } -instret:442 PC:0x1ffff00000000000000000000800013da instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2799 -instret:443 PC:0x1ffff00000000000000000000800013de instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2799 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 3ffffffffffffbb80fff00001fffff44000000 - 28000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93da } - 28000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 28000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 28000 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 28000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -instret:444 PC:0x1ffff00000000000000000000800013e2 instr:0xc7250513 iType:Alu [doCommitNormalInst [0]] 2800 -instret:445 PC:0x1ffff00000000000000000000800013e6 instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2800 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 3ffffffffffffbb00fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 28010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h002 } - 28010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 28010 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000834000000001fffff44000000 - 28010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } - 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93da } -[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 28010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:446 PC:0x1ffff00000000000000000000800013ea instr:0x0040006f iType:J [doCommitNormalInst [0]] 2801 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h002 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h93e6 } - 28020 : [doRespLdForward] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000008000000001fffff44000000 - 28020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 28020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 28030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 28030 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000008000000001fffff44000000 - 28030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93e6 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 28040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 28040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 28040 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000020000834000000001fffff44000000 - 28040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 28040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 000000002000083c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28050 : [doRespLdForward] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000020000834000000001fffff44000000 - 28050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020f0 o: 'h00000000800020f0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800020d0 -After delta: vaddr = 0x800020d0 - 28050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28060 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 28060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 28060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h00a, globalTaken: False, localTaken: False, pcIndex: 'h1fa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f88 -After delta: vaddr = 0x80000f88 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffad4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28170 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } - 28170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h93ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93ee } - 28180 : [Ld resp] 'h08; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } } - 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 77 <= 00000000200003ec000000001fffff44000000 - 28190 : [doRespLdMem] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6b <= 0000000020040814000000001fffff44000000 - 28190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h000, globalTaken: False, localTaken: False, pcIndex: 'h2a3 }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 78 <= 000000002000094d000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102050 -After delta: vaddr = 0x80102050 - 28200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 79 <= 0000000020000802000000001fffff44000000 - 28210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102050, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 28210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:447 PC:0x1ffff00000000000000000000800013ee instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2821 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffaac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28220 : [doFinishMem] DTlbResp { resp: <'h0000000080102050,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102050 o: 'h0000000080102050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102050, check_high: 'h00000000080102058, check_inclusive: True } }, specBits: 'h000 } - 28220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080102050, shiftedBE: tagged DataMemAccess , pcHash: 'h93f2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 28220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28230 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h001 } - 28230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h953c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080102050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h93f2 } - 28230 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } - 28230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 05 <= 0000000020000957000000001fffff44000000 - 28240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h001 } - 28240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9542 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28240 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 6c <= 0000000000000000000000001fffff44000000 - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h953c } - 28240 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } - 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 28240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 58 <= 0000000020000802000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080102050, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28250 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7a <= 0000000020000834000000001fffff44000000 - 28250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9542 } - 28250 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } } - 28250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 28250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28260 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h005 } - 28260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h9564 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28260 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 7d <= 0000000000000008000000001fffff44000000 - 28260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 28260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } -instret:448 PC:0x1ffff00000000000000000000800013f2 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2826 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28270 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h005 } - 28270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080002008, shiftedBE: tagged DataMemAccess , pcHash: 'h956a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9564 } - 28270 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } - 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7b <= 3ffffffffffffbb80fff00001fffff44000000 - 28280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h004 } - 28280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h956c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28280 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0a <= 0000000020000834000000001fffff44000000 - 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956a } - 28280 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } - 28280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h006 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f78 -After delta: vaddr = 0x80000f78 - 28280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } -instret:449 PC:0x1ffff00000000000000000000800013f4 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2828 -instret:450 PC:0x1ffff00000000000000000000800013f6 instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2828 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 7c <= 3ffffffffffffbb00fff00001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28290 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 44 <= 0000000020000834000000001fffff44000000 - 28290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h006 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h956c } - 28290 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } - 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 28290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:451 PC:0x1ffff0000000000000000000080001532 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2829 -instret:452 PC:0x1ffff0000000000000000000080001534 instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2829 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h004 } - 28300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h9578 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28300 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 0c <= 0000000000000008000000001fffff44000000 - 28300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h004 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h004 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 28300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } -instret:453 PC:0x1ffff0000000000000000000080001538 instr:0xad458593 iType:Alu [doCommitNormalInst [0]] 2830 -instret:454 PC:0x1ffff000000000000000000008000153c instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2830 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h004, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h004, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle - 28310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 28310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9578 } - 28310 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } - 28310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f80 -After delta: vaddr = 0x80000f80 - 28310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:455 PC:0x1ffff000000000000000000008000153e instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2831 -instret:456 PC:0x1ffff0000000000000000000080001540 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2831 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 28320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h957c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 28320 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5b <= 0000000000000008000000001fffff44000000 - 28320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h55, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002008 -After delta: vaddr = 0x80002008 - 28320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:457 PC:0x1ffff0000000000000000000080001542 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2832 -instret:458 PC:0x1ffff0000000000000000000080001546 instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2832 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 55 <= 000000002000083c000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080002008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } - 28330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h9582 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 28330 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 08 <= 0000000020000834000000001fffff44000000 - 28330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020f0 o: 'h00000000800020f0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002008, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 28330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:459 PC:0x1ffff000000000000000000008000154a instr:0x0120006f iType:J [doCommitNormalInst [0]] 2833 -instret:460 PC:0x1ffff000000000000000000008000155c instr:0x00001517 iType:Auipc [doCommitNormalInst [1]] 2833 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28340 : [doFinishMem] DTlbResp { resp: <'h0000000080002008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002008 o: 'h0000000080002008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002008, check_high: 'h00000000080002010, check_inclusive: True } }, specBits: 'h000 } - 28340 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4f <= 0000000020000834000000001fffff44000000 - 28340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x800020d0 -After delta: vaddr = 0x800020d0 - 28340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:461 PC:0x1ffff0000000000000000000080001560 instr:0xaac50593 iType:Alu [doCommitNormalInst [0]] 2834 -instret:462 PC:0x1ffff0000000000000000000080001564 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2834 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } - 28350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000020 o: 'h0000000000000020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020d0, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa8 -After delta: vaddr = 0x80000fa8 - 28350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:463 PC:0x1ffff0000000000000000000080001566 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2835 -instret:464 PC:0x1ffff000000000000000000008000156a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2835 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28360 : [doFinishMem] DTlbResp { resp: <'h00000000800020d0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800020d0 o: 'h00000000800020d0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800020d0, check_high: 'h000000000800020d8, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9566 } - 28360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000f98 -After delta: vaddr = 0x80000f98 - 28360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -instret:465 PC:0x1ffff000000000000000000008000156c instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2836 -instret:466 PC:0x1ffff0000000000000000000080001570 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2836 -calling cycle -[RFile] wr_ 0: r 54 <= 0000000020000836000000001fffff44000000 -[RFile] wr_ 1: r 4d <= 00000000200003ec000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28370 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa8 o: 'h0000000080000fa8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa8, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } - 28370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000fa8, shiftedBE: tagged DataMemAccess , pcHash: 'h9594 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } - 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9566 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fa0 -After delta: vaddr = 0x80000fa0 - 28370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } -instret:467 PC:0x1ffff0000000000000000000080001572 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2837 -instret:468 PC:0x1ffff0000000000000000000080001574 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2837 -calling cycle - 28380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9572 } - 28380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080000fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9594 } - 28380 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } } - 28380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -instret:469 PC:0x1ffff0000000000000000000080001578 instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2838 -instret:470 PC:0x1ffff000000000000000000008000157c instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2838 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fa8, check_inclusive: True } }, specBits: 'h000 } - 28390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h9596 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28390 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4c <= 000000002000045b800000001fffff44000000 - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9572 } -[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } -instret:471 PC:0x1ffff0000000000000000000080001580 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2839 -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800020d0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9580 } - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9596 } - 28400 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } } - 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800020d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -instret:472 PC:0x1ffff0000000000000000000080001582 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2840 -instret:473 PC:0x1ffff0000000000000000000080001586 instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2840 -calling cycle - 28410 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 01 <= 0000000020000400000000001fffff44000000 - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800020d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800020d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9580 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:474 PC:0x1ffff0000000000000000000080001588 instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2841 -instret:475 PC:0x1ffff000000000000000000008000158c instr:0x0040006f iType:J [doCommitNormalInst [1]] 2841 -calling cycle -[ALU redirect - 1] 'h1ffff000000000000000000008000116e; 'h1; InstTag { way: 'h1, ptr: 'h10, t: 'h21 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h9588 } - 28420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -calling cycle - 28430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } -[ROB incorrectSpec] 'h1 ; InstTag { way: 'h1, ptr: 'h10, t: 'h21 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; -calling cycle - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9588 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 28450 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h9590 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 28450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace - 28450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } -calling cycle - 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9590 } - 28460 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } - 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle - 28470 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002150, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } - 28470 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 43 <= 0000000020000836000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False }, paddr: 'h0000000080000fa8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:476 PC:0x1ffff0000000000000000000080001590 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2849 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:477 PC:0x1ffff0000000000000000000080001594 instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2850 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffeac }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 28510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fc0 -After delta: vaddr = 0x80000fc0 -instret:478 PC:0x1ffff0000000000000000000080001596 instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2851 -instret:479 PC:0x1ffff0000000000000000000080001598 instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2851 - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 28520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:480 PC:0x1ffff000000000000000000008000159a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2852 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 40 <= 0000000020000836000000001fffff44000000 - 28530 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fc8, check_inclusive: True } }, specBits: 'h000 } - 28530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h9170 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 28530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9170 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 60 <= 000000002004085d000000001fffff44000000 - 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9170 } - 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9170 } - 28540 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } } - 28540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80102020 -After delta: vaddr = 0x80102020 - 28540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:481 PC:0x1ffff000000000000000000008000116e instr:0x000085aa iType:Alu [doCommitNormalInst [0]] 2854 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe76 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 5c <= 0000000020040808000000001fffff44000000 - 28550 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 5e <= 0000000000000000000000001fffff44000000 - 28550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102020, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe4 -After delta: vaddr = 0x80000fe4 - 28550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe4, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0cb }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 28560 : [doFinishMem] DTlbResp { resp: <'h0000000080102020,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102020, check_high: 'h00000000080102028, check_inclusive: True } }, specBits: 'h000 } - 28560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe4, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe4 -After delta: vaddr = 0x80000fe4 - 28560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000020000862800000001fffff44000000 - 28570 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } - 28570 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fe4, shiftedBE: tagged DataMemAccess , pcHash: 'h9186 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe4, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 - 28570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } -instret:482 PC:0x1ffff0000000000000000000080001170 instr:0xfc043503 iType:Ld [doCommitNormalInst [0]] 2857 -instret:483 PC:0x1ffff0000000000000000000080001174 instr:0x00101617 iType:Auipc [doCommitNormalInst [1]] 2857 -calling cycle -[RFile] wr_ 0: r 45 <= 0000000020000800000000001fffff44000000 - 28580 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } - 28580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } - 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } - 28580 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -instret:484 PC:0x1ffff0000000000000000000080001178 instr:0xeac60613 iType:Alu [doCommitNormalInst [0]] 2858 -instret:485 PC:0x1ffff000000000000000000008000117c instr:0x0000e20c iType:St [doCommitNormalInst [1]] 2858 -calling cycle - 28590 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080102020, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h917c } - 28590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9192 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 28590 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 000000000847254b800000001fffff44000000 - 28590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } -instret:486 PC:0x1ffff000000000000000000008000117e instr:0xfea42223 iType:St [doCommitNormalInst [0]] 2859 -instret:487 PC:0x1ffff0000000000000000000080001182 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2859 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } - 28600 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 28600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 28600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080102020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917c } -calling cycle - 28610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000000c00000001fffff44000000 - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080102020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917c } - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080102020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917c } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h917e } - 28620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fe4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917e } -calling cycle - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fe4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917e } - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fe4, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h917e } -[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 28630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - 28950 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002150, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } -calling cycle - 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: - 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } - 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe76 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - 29330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe4 -After delta: vaddr = 0x80000fe4 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h0ca }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } -calling cycle - 29340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe4, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 41 <= 0000000020000862800000001fffff44000000 - 29350 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } - 29350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fe4, shiftedBE: tagged DataMemAccess , pcHash: 'h9186 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80002000 -After delta: vaddr = 0x80002000 - 29350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 45 <= 0000000020000800000000001fffff44000000 - 29360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9186 } - 29360 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } - 29360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffcc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29370 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002004, check_inclusive: True } }, specBits: 'h000 } - 29370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess , pcHash: 'h9192 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29370 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000 - 29370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fcc -After delta: vaddr = 0x80000fcc - 29370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffcc, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - 29370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Lt, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h10d }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 1: r 4a <= 0000000000000000000000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fcc, write: True, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } - 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9192 } - 29380 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } - 29380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 29380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffcc, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fcc -After delta: vaddr = 0x80000fcc - 29380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000001a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29390 : [doFinishMem] DTlbResp { resp: <'h0000000080000fcc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fcc, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h001 } - 29390 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 53 <= 0000000000000000c00000001fffff44000000 - 29390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffcc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fcc, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc - 29390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } -Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe8 -After delta: vaddr = 0x80000fe8 -instret:488 PC:0x1ffff0000000000000000000080001186 instr:0xfe442503 iType:Ld [doCommitNormalInst [0]] 2939 -instret:489 PC:0x1ffff000000000000000000008000118a instr:0x00001597 iType:Auipc [doCommitNormalInst [1]] 2939 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 29400 : [doFinishMem] DTlbResp { resp: <'h0000000080000fcc,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fcc o: 'h0000000080000fcc b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fcc, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h001 } - 29400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fcc, shiftedBE: tagged DataMemAccess , pcHash: 'h9212 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: False, data: } } - 29400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe8, write: False, capStore: False, potentialCapLoad: False } -L1 TLB inc -instret:490 PC:0x1ffff000000000000000000008000118e instr:0xe7658593 iType:Alu [doCommitNormalInst [0]] 2940 -calling cycle - 29410 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe8, check_high: 'h00000000080000fec, check_inclusive: True } }, specBits: 'h001 } - 29410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fe8, shiftedBE: tagged DataMemAccess , pcHash: 'h9216 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 29410 : [doRespLdForward] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 - 29410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9216 } -instret:491 PC:0x1ffff0000000000000000000080001192 instr:0x0000418c iType:Ld [doCommitNormalInst [0]] 2941 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe08 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h019, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fcc, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -[ALU redirect - 0] 'h1ffff000000000000000000008000119c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9216 } - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h9216 } - 29420 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } - 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 23450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:157 PC:0x1ffff000000000000000000008000022e instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2345 +instret:158 PC:0x1ffff0000000000000000000080000230 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2345 calling cycle [ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; calling cycle - 29440 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } -instret:492 PC:0x1ffff0000000000000000000080001194 instr:0x00b54463 iType:Br [doCommitNormalInst [0]] 2944 +instret:159 PC:0x1ffff0000000000000000000080000232 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2347 calling cycle calling cycle calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 23520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00101000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffe80 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } -calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle - 29970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1f}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000003ff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -calling cycle -[RFile] wr_ 0: r 4a <= 0000000020040868000000001fffff44000000 - 29980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } + 23530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80102020 -After delta: vaddr = 0x80102020 - 29980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe4, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000034 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } - [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 23530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 64 <= 0000000020040808000000001fffff44000000 - 29990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080102020, write: False, capStore: False, potentialCapLoad: False } + 23540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } L1 TLB inc - 29990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe4, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 23540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } Decoded delta from register = 0 -Before delta: vaddr = 0x80000fe4 -After delta: vaddr = 0x80000fe4 -instret:493 PC:0x1ffff000000000000000000008000119c instr:0x0040006f iType:J [doCommitNormalInst [0]] 2999 -instret:494 PC:0x1ffff00000000000000000000800011a0 instr:0x00101517 iType:Auipc [doCommitNormalInst [1]] 2999 - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 30000 : [doFinishMem] DTlbResp { resp: <'h0000000080102020,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080102020 o: 'h0000000080102020 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080102020, check_high: 'h00000000080102028, check_inclusive: True } }, specBits: 'h000 } - 30000 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080102020, shiftedBE: tagged DataMemAccess , pcHash: 'h91a8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe4, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe4, write: False, capStore: False, potentialCapLoad: False } + 23550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 23550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } L1 TLB inc - 30000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080102020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91a8 } -instret:495 PC:0x1ffff00000000000000000000800011a4 instr:0xe8050513 iType:Alu [doCommitNormalInst [0]] 3000 + 23550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 1: r 67 <= 00000000000000ffc00000001fffff44000000 - 30010 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe4,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe4 o: 'h0000000080000fe4 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe4, check_high: 'h00000000080000fe8, check_inclusive: True } }, specBits: 'h000 } - 30010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fe4, shiftedBE: tagged DataMemAccess , pcHash: 'h91aa } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040081, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080102020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91a8 } - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080102020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91a8 } - 30010 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } - 30010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid - 30010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91aa } -calling cycle -[RFile] wr_ 0: r 65 <= 0ffc00000000000003ff00001fffff44000000 - 30020 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 63 <= 0000000020000836000000001fffff44000000 - 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91aa } - 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fe4, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91aa } - 30020 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } } - 30020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid -calling cycle -[RFile] wr_ 0: r 70 <= 000000002000046e800000001fffff44000000 -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080102020, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } - 30030 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } -[RFile] wr_ 3: r 61 <= 0000000000000000000000001fffff44000000 -calling cycle -[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000fe4, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } -instret:496 PC:0x1ffff00000000000000000000800011a8 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3004 -calling cycle - 30050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } -instret:497 PC:0x1ffff00000000000000000000800011aa instr:0xfe442583 iType:Ld [doCommitNormalInst [0]] 3005 -calling cycle -[RFile] wr_ 1: r 62 <= 0000000000000000000000001fffff44000000 - 30060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } + 23560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 23560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81f0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 23560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } Decoded delta from register = 0 -Before delta: vaddr = 0x800020d8 -After delta: vaddr = 0x800020d8 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 23560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:160 PC:0x1ffff00000000000000000000800001ec instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2356 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -[RFile] wr_ 0: r 66 <= 0000000020000836000000001fffff44000000 - 30070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h3ff0000000000000 o: 'h3ff0000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } -DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000000800020d8, write: True, capStore: False, potentialCapLoad: False } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81ec } + 23570 : [doRespLdForward] 'h15; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 61 <= 7ffdff00200004021008ffff1ffff804099008 + 23570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } L1 TLB inc -instret:498 PC:0x1ffff00000000000000000000800011ae instr:0x0000058e iType:Alu [doCommitNormalInst [0]] 3007 + 23570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 23570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ec } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23580 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 23580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h81fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ec } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ec } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h61, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 23580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 23580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } +calling cycle + 23590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 23590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8200 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 23590 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 23590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 23590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } +instret:161 PC:0x1ffff00000000000000000000800001f0 instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2359 +calling cycle +[RFile] wr_ 1: r 65 <= 00000000200003f0000000001fffff44000000 + 23600 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 23600 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000000000000000000001fffff44000000 + 23600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 23600 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 23600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 23610 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 23610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8202 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23610 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 000000002000001b000000001fffff44000000 + 23610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } +instret:162 PC:0x1ffff00000000000000000000800001f4 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2361 +instret:163 PC:0x1ffff00000000000000000000800001f8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2361 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81f4 } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 23620 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 23620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f4 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23630 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000020000400000000001fffff44000000 + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f4 } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 23730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 23740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 23740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 23750 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 23750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h81fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 23750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } +calling cycle + 23760 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 23760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8200 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 23760 : [Ld resp] 'h00; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 23760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } +calling cycle +[RFile] wr_ 1: r 65 <= 00000000200003f0000000001fffff44000000 + 23770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 23770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8202 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 23770 : [doRespLdMem] 'h00; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 5b <= 7ffdff00200004021008ffff1ffff804099008 + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 23770 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 23780 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 000000002000001b000000001fffff44000000 + 23780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 23780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 23780 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 23780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 23790 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000020000400000000001fffff44000000 +instret:164 PC:0x1ffff00000000000000000000800001fc instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2379 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:165 PC:0x1ffff0000000000000000000080000200 instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 2380 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000006c; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:166 PC:0x1ffff0000000000000000000080000202 instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 2381 +instret:167 PC:0x1ffff0000000000000000000080000204 instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 2381 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:168 PC:0x1ffff0000000000000000000080000206 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2383 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000da }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 23900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h5b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 +calling cycle + 23910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc +calling cycle +[RFile] wr_ 1: r 43 <= 0000000000000004000000001fffff44000000 + 23920 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } +calling cycle +[RFile] wr_ 1: r 0d <= 000000002000001c800000001fffff44000000 +instret:169 PC:0x1ffff000000000000000000008000006c instr:0xfca44823 iType:St [doCommitNormalInst [0]] 2393 +instret:170 PC:0x1ffff0000000000000000000080000070 instr:0x00004541 iType:Alu [doCommitNormalInst [1]] 2393 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000043 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 68 <= 000000002000001e800000001fffff44000000 +[ALU redirect - 0] 'h1ffff000000000000000000008000014c; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h806c } + 23940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806c } +instret:171 PC:0x1ffff0000000000000000000080000072 instr:0x00000097 iType:Auipc [doCommitNormalInst [0]] 2394 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle + 23960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806c } + 23960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806c } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 23960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:172 PC:0x1ffff0000000000000000000080000076 instr:0x0da080e7 iType:Jr [doCommitNormalInst [0]] 2396 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff90 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000068, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 24020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000060, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 00000000200003d4000000001fffff44000000 + 24030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000007a o: 'h000000008000007a b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 24030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h02, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000102 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6f <= 00000000200003f0000000001fffff44000000 + 24040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 24040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:173 PC:0x1ffff000000000000000000008000014c instr:0x00007159 iType:Alu [doCommitNormalInst [0]] 2404 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24050 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 24050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000058, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:174 PC:0x1ffff000000000000000000008000014e instr:0x0000f486 iType:St [doCommitNormalInst [0]] 2405 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 66 <= 0000000020000057000000001fffff44000000 + 24060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h814e } + 24060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 24060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000050, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } +instret:175 PC:0x1ffff0000000000000000000080000150 instr:0x0000f0a2 iType:St [doCommitNormalInst [0]] 2406 +instret:176 PC:0x1ffff0000000000000000000080000152 instr:0x00001880 iType:Alu [doCommitNormalInst [1]] 2406 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 00000000200003bc000000001fffff44000000 +[RFile] wr_ 1: r 72 <= 0000000020000059000000001fffff44000000 + 24070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 24070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h8158 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000164 o: 'h0000000080000164 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } + 24070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h814e } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h6f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 +instret:177 PC:0x1ffff0000000000000000000080000154 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2407 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24080 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8150 } + 24080 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000000000004000000001fffff44000000 + 24080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h139 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 41 <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24090 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8150 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 24090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8154 } + 24100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 24100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +instret:178 PC:0x1ffff0000000000000000000080000158 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2410 +instret:179 PC:0x1ffff000000000000000000008000015c instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2410 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Subw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7a <= 0000000000000001c00000001fffff44000000 + 24110 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 24110 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8154 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 +instret:180 PC:0x1ffff0000000000000000000080000160 instr:0x102080e7 iType:Jr [doCommitNormalInst [0]] 2411 +instret:181 PC:0x1ffff000000000000000000008000025e instr:0x0000711d iType:Alu [doCommitNormalInst [1]] 2411 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000007 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24120 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 24120 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h826a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24120 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:182 PC:0x1ffff0000000000000000000080000260 instr:0x0000ec86 iType:St [doCommitNormalInst [0]] 2412 +instret:183 PC:0x1ffff0000000000000000000080000262 instr:0x0000e8a2 iType:St [doCommitNormalInst [1]] 2412 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h05, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24130 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8260 } + 24130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8286 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24130 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 79 <= 0000000000000004000000001fffff44000000 + 24130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } +instret:184 PC:0x1ffff0000000000000000000080000264 instr:0x00001080 iType:Alu [doCommitNormalInst [0]] 2413 +instret:185 PC:0x1ffff0000000000000000000080000266 instr:0xfea43023 iType:St [doCommitNormalInst [1]] 2413 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000000000000000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24140 : [doRespLdForward] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000004000000001fffff44000000 + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8260 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8262 } + 24150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 24150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } +instret:186 PC:0x1ffff000000000000000000008000026a instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 2415 +instret:187 PC:0x1ffff000000000000000000008000026e instr:0x0000451d iType:Alu [doCommitNormalInst [1]] 2415 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffd6c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8262 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7b <= 3ffffffffffffffc0fff00001fffff44000000 + 24170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h004 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8266 } + 24170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h829c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } +instret:188 PC:0x1ffff0000000000000000000080000270 instr:0x00b57463 iType:Br [doCommitNormalInst [0]] 2417 +instret:189 PC:0x1ffff0000000000000000000080000274 instr:0x0120006f iType:J [doCommitNormalInst [1]] 2417 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h15e }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 0000000000000000000000001fffff44000000 + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 24180 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 24180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 24180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa8, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } +instret:190 PC:0x1ffff0000000000000000000080000286 instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2418 +instret:191 PC:0x1ffff000000000000000000008000028a instr:0x00004581 iType:Alu [doCommitNormalInst [1]] 2418 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 47 <= 00000000200044a9000000001fffff44000000 +[RFile] wr_ 1: r 05 <= 0000000000000004000000001fffff44000000 + 24190 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 000000000000000a000000001fffff44000000 + 24190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8266 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h7c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + 24190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:192 PC:0x1ffff000000000000000000008000028c instr:0x00009d89 iType:Alu [doCommitNormalInst [0]] 2419 +instret:193 PC:0x1ffff000000000000000000008000028e instr:0x0000899d iType:Alu [doCommitNormalInst [1]] 2419 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc0e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 0000000000000006000000001fffff44000000 +[RFile] wr_ 1: r 01 <= 0000000020004404000000001fffff44000000 + 24200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h002 } + 24200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h82b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } +instret:194 PC:0x1ffff0000000000000000000080000290 instr:0x0000952e iType:Alu [doCommitNormalInst [0]] 2420 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24210 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 24210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000028 o: 'h0000000000000028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } + 24210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b4 } + 24210 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } } + 24210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 +instret:195 PC:0x1ffff0000000000000000000080000292 instr:0x00000521 iType:Alu [doCommitNormalInst [0]] 2421 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 00000000200003d4000000001fffff44000000 + 24220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 24220 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 23fffbfe0400000008ff00001fffff44000000 + 24220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:196 PC:0x1ffff0000000000000000000080000294 instr:0xfaa43423 iType:St [doCommitNormalInst [0]] 2422 +instret:197 PC:0x1ffff0000000000000000000080000298 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2422 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h206 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 69 <= 00000000200044fe800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8294 } + 24230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 18874335 +Before delta: vaddr = 0x7810000000 +After delta: vaddr = 0x78111fffdf + 24230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8294 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5c <= 0000000020004402000000001fffff44000000 + 24240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h8fffeff810000000 o: 'h8fffeff810000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h00000078111fffdf o: 'h8ff00078111fffdf b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h00000078111fffdf, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8294 } + 24240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8294 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffbe6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24250 : [doFinishMem] DTlbResp { resp: <'h00000078111fffdf,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000078111fffdf o: 'h8ff00078111fffdf b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: True, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000078111fffdf, check_high: 'h000000078111fffe7, check_inclusive: True } }, specBits: 'h000 } + 24250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24260 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h001 } + 24260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h8402 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 51 <= 0000000020004508800000001fffff44000000 +[doDeqLdQ_fault] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h00000078111fffdf, isMMIO: True, shiftedBE: tagged DataMemAccess , fault: tagged Valid tagged Exception excLoadAddrMisaligned, allowCap: False, killed: tagged Invalid } + 24270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h001 } + 24270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8408 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 24270 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 24270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 0000000020004402000000001fffff44000000 + 24280 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 000000002000040a000000001fffff44000000 + 24280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24290 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h003 } + 24290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h842a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24290 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 000000000000000a000000001fffff44000000 + 24290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24300 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h003 } + 24300 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h8430 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 24300 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 24300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 75 <= 3fffffffffffffca0fff00001fffff44000000 + 24310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h003 } + 24310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8432 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24310 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 000000002000040a000000001fffff44000000 + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 24310 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 24310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4c <= 3fffffffffffffc20fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24320 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 000000002000040a000000001fffff44000000 + 24320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h007 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 24320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h003 } + 24330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h843e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24330 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 000000000000000a000000001fffff44000000 + 24330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 24330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } + 24340 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 000000000000000a000000001fffff44000000 + 24340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } + 24350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8442 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 53 <= 0000000020000414000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24360 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 000000002000040a000000001fffff44000000 + 24360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001050 o: 'h0000000080001050 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 24360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24370 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h001 } + 24370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001028 +After delta: vaddr = 0x80001028 + 24370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h001 } + 24380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8448 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000028 o: 'h0000000000000028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001028, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 24380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h0b6 }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24390 : [doFinishMem] DTlbResp { resp: <'h0000000080001028,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001028, check_high: 'h00000000080001030, check_inclusive: True } }, specBits: 'h001 } + 24390 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 000000002000040a000000001fffff44000000 + 24390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 24390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0d <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 24400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8456 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 24400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 24410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h001 } + 24410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h845a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 24410 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 24410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h00f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 000000002000040c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h001 } + 24420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h845c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24420 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 3fffc000010204030fff00001fffff44000000 + 24420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 24420 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff68 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h001 } + 24430 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000059000000001fffff44000000 + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 24430 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h01f, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24440 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 00000000200003f0000000001fffff44000000 + 24440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6c <= 0000000020000063800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 24450 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000020000065800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffff00000408100c o: 'hffff00000408100c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24460 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 24460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRAM, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h017, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 00000000200003c8000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 24470 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 24470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4f <= 00000000200003d4000000001fffff44000000 + 24480 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h001 } + 24480 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 24480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffef2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h005 } + 24490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8182 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24490 : [doRespLdForward] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 3fffc000010204030fff00001fffff44000000 + 24490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 24490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Xor, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h005 } + 24500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h818a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24500 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 3fffc000010204030fff00001fffff44000000 + 24500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000196 o: 'h0000000080000196 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 24500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000020004443800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h005 } + 24510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + 24510 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 24510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 24510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle + 24530 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ef8 +After delta: vaddr = 0x80000ef8 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffd6c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ef8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24630 : [doFinishMem] DTlbResp { resp: <'h0000000080000ef8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ef8 o: 'h0000000080000ef8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ef8, check_high: 'h00000000080000f00, check_inclusive: True } }, specBits: 'h000 } + 24630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000ef8, shiftedBE: tagged DataMemAccess , pcHash: 'h829c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h15d }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 47 <= 00000000200044a9000000001fffff44000000 + 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080000ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h829c } + 24640 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } } + 24640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 24640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h41, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h1c, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000013c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 0000000020004404000000001fffff44000000 + 24650 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 44 <= 0000000000000006000000001fffff44000000 + 24650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 24650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffc0e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False }, paddr: 'h0000000080000ef8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 24660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24660 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 24670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h82b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24670 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:198 PC:0x1ffff000000000000000000008000029c instr:0xfa843503 iType:Ld [doCommitNormalInst [0]] 2467 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h006, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 08 <= 00000000200003d4000000001fffff44000000 + 24680 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 24680 : [doRespLdForward] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000020004404000000001fffff44000000 + 24680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Ltu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h206 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 69 <= 00000000200044fe800000001fffff44000000 + 24690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011010 +After delta: vaddr = 0x80011010 + 24690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:199 PC:0x1ffff00000000000000000000800002a0 instr:0xfca43423 iType:St [doCommitNormalInst [0]] 2469 +instret:200 PC:0x1ffff00000000000000000000800002a4 instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 2469 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 0000000020004402000000001fffff44000000 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82a0 } + 24700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011010, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +instret:201 PC:0x1ffff00000000000000000000800002a8 instr:0xd6c50513 iType:Alu [doCommitNormalInst [0]] 2470 +instret:202 PC:0x1ffff00000000000000000000800002ac instr:0xfca43c23 iType:St [doCommitNormalInst [1]] 2470 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffbe6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24710 : [doFinishMem] DTlbResp { resp: <'h0000000080011010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011010, check_high: 'h00000000080011018, check_inclusive: True } }, specBits: 'h000 } + 24710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080011010, shiftedBE: tagged DataMemAccess , pcHash: 'h82b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } +instret:203 PC:0x1ffff00000000000000000000800002b0 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2471 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24720 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h002 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h82ac } + 24720 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h8402 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82b8 } + 24720 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 24720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } +instret:204 PC:0x1ffff00000000000000000000800002b4 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2472 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 51 <= 0000000020004508800000001fffff44000000 + 24730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h002 } + 24730 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8408 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24730 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 0000000000000000000000001fffff44000000 + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8402 } + 24730 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h007 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 0000000020004402000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080011010, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24740 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 60 <= 000000002000040a000000001fffff44000000 + 24740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8408 } + 24740 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } } + 24740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ac } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24750 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h003 } + 24750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h842a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24750 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 56 <= 0000000000000006000000001fffff44000000 + 24750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ac } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h82ac } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } +instret:205 PC:0x1ffff00000000000000000000800002b8 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2475 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24760 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h003 } + 24760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080011008, shiftedBE: tagged DataMemAccess , pcHash: 'h8430 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842a } + 24760 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 3fffffffffffffca0fff00001fffff44000000 + 24770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h001 } + 24770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h8432 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24770 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 59 <= 000000002000040a000000001fffff44000000 + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080011008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8430 } + 24770 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } } + 24770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f18 +After delta: vaddr = 0x80000f18 + 24770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8432 } +instret:206 PC:0x1ffff00000000000000000000800002ba instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 2477 +instret:207 PC:0x1ffff00000000000000000000800002bc instr:0x13c0006f iType:J [doCommitNormalInst [1]] 2477 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4c <= 3fffffffffffffc20fff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24780 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5d <= 000000002000040a000000001fffff44000000 + 24780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f18, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8432 } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8432 } + 24780 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 24780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:208 PC:0x1ffff00000000000000000000800003f8 instr:0x00008522 iType:Alu [doCommitNormalInst [0]] 2478 +instret:209 PC:0x1ffff00000000000000000000800003fa instr:0x00011597 iType:Auipc [doCommitNormalInst [1]] 2478 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f18,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f18 o: 'h0000000080000f18 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f18, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h001 } + 24790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f18, shiftedBE: tagged DataMemAccess , pcHash: 'h843e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24790 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4e <= 0000000000000006000000001fffff44000000 + 24790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 24790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h843e } +instret:210 PC:0x1ffff00000000000000000000800003fe instr:0xc0e58593 iType:Alu [doCommitNormalInst [0]] 2479 +instret:211 PC:0x1ffff0000000000000000000080000402 instr:0x0000618c iType:Ld [doCommitNormalInst [1]] 2479 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 24800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 24800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h843e } + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080000f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h843e } + 24800 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 24800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 24800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:212 PC:0x1ffff0000000000000000000080000404 instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2480 +instret:213 PC:0x1ffff0000000000000000000080000406 instr:0x00001501 iType:Alu [doCommitNormalInst [1]] 2480 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 24810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 24810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8442 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24810 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 4b <= 0000000000000006000000001fffff44000000 + 24810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011008 +After delta: vaddr = 0x80011008 + 24810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:214 PC:0x1ffff0000000000000000000080000408 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2481 +instret:215 PC:0x1ffff000000000000000000008000040c instr:0x00b56463 iType:Br [doCommitNormalInst [1]] 2481 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 53 <= 0000000020000410000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080011008, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 24820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8448 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 24820 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5a <= 000000002000040a000000001fffff44000000 + 24820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001040 o: 'h0000000080001040 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011008, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 24820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:216 PC:0x1ffff0000000000000000000080000410 instr:0x0120006f iType:J [doCommitNormalInst [0]] 2482 +instret:217 PC:0x1ffff0000000000000000000080000422 instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 2482 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24830 : [doFinishMem] DTlbResp { resp: <'h0000000080011008,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011008 o: 'h0000000080011008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011008, check_high: 'h00000000080011010, check_inclusive: True } }, specBits: 'h000 } + 24830 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 000000002000040a000000001fffff44000000 + 24830 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h002 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001028 +After delta: vaddr = 0x80001028 + 24830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:218 PC:0x1ffff0000000000000000000080000426 instr:0xbe650593 iType:Alu [doCommitNormalInst [0]] 2483 +instret:219 PC:0x1ffff000000000000000000008000042a instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2483 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24840 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 24840 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8456 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000018 o: 'h0000000000000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001028, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 24840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } +instret:220 PC:0x1ffff000000000000000000008000042c instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2484 +instret:221 PC:0x1ffff0000000000000000000080000430 instr:0x00006188 iType:Ld [doCommitNormalInst [1]] 2484 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f18, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24850 : [doFinishMem] DTlbResp { resp: <'h0000000080001028,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080001028 o: 'h0000000080001028 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001028, check_high: 'h00000000080001030, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h842c } + 24850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 24850 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 24850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 24850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842c } +instret:222 PC:0x1ffff0000000000000000000080000432 instr:0xfc843603 iType:Ld [doCommitNormalInst [0]] 2485 +instret:223 PC:0x1ffff0000000000000000000080000436 instr:0x00009532 iType:Alu [doCommitNormalInst [1]] 2485 +calling cycle +[RFile] wr_ 0: r 0d <= 00000000200003d4000000001fffff44000000 +[RFile] wr_ 1: r 50 <= 000000002000040c000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 24860 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h845a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24860 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 3fffc000010204030fff00001fffff44000000 + 24860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842c } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h842c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 24860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } +instret:224 PC:0x1ffff0000000000000000000080000438 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2486 +instret:225 PC:0x1ffff000000000000000000008000043a instr:0x0040006f iType:J [doCommitNormalInst [1]] 2486 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 24870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080011008, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8438 } + 24870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 24870 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 24870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080011008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8438 } +instret:226 PC:0x1ffff000000000000000000008000043e instr:0xfc843503 iType:Ld [doCommitNormalInst [0]] 2487 +instret:227 PC:0x1ffff0000000000000000000080000442 instr:0xfd043583 iType:Ld [doCommitNormalInst [1]] 2487 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 24880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h845c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 24880 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000059000000001fffff44000000 + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080011008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8438 } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080011008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8438 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } +instret:228 PC:0x1ffff0000000000000000000080000446 instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2488 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001028, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8446 } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 24890 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } +instret:229 PC:0x1ffff0000000000000000000080000448 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2489 +instret:230 PC:0x1ffff000000000000000000008000044c instr:0x00000521 iType:Alu [doCommitNormalInst [1]] 2489 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 24900 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 00000000200003f0000000001fffff44000000 + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8446 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:231 PC:0x1ffff000000000000000000008000044e instr:0xfea43423 iType:St [doCommitNormalInst [0]] 2490 +instret:232 PC:0x1ffff0000000000000000000080000452 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2490 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000164; 'h0; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h844e } + 24910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 24910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 24910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h844e } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h13, t: 'h27 } ; 'h1 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h844e } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h844e } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 24930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 25020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000058, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000060 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000058, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000050, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 25040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8456 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000058, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000050, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 25040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } +calling cycle + 25050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h845a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000050, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000ef0 o: 'h0000000080000ef0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8456 } + 25050 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } +calling cycle +[RFile] wr_ 1: r 0d <= 00000000200003d4000000001fffff44000000 + 25060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 25060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h845c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25060 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 62 <= 000000002000040c000000001fffff44000000 + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845a } + 25060 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 25060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25070 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000059000000001fffff44000000 + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h845c } + 25070 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25080 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 00000000200003f0000000001fffff44000000 + 25080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:233 PC:0x1ffff0000000000000000000080000456 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2508 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:234 PC:0x1ffff000000000000000000008000045a instr:0x000060e6 iType:Ld [doCommitNormalInst [0]] 2509 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 1] 'h1ffff0000000000000000000080000164; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } + 25100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: True } +L1 TLB inc + 25100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 25100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:235 PC:0x1ffff000000000000000000008000045c instr:0x00006446 iType:Ld [doCommitNormalInst [0]] 2510 +instret:236 PC:0x1ffff000000000000000000008000045e instr:0x00006125 iType:Alu [doCommitNormalInst [1]] 2510 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:237 PC:0x1ffff0000000000000000000080000460 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2512 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25160 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h155, globalTaken: False, localTaken: False, pcIndex: 'h0b6 }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25170 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h62, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 25170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25180 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + 25180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25190 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 25190 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f90 +After delta: vaddr = 0x80000f90 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25200 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h000 } + 25200 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8168 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h003 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f90, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:238 PC:0x1ffff0000000000000000000080000164 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2520 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff68 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h0d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25210 : [doFinishMem] DTlbResp { resp: <'h0000000080000f90,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f90, check_high: 'h00000000080000f98, check_inclusive: True } }, specBits: 'h003 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8164 } + 25210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f90, shiftedBE: tagged DataMemAccess , pcHash: 'h8182 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25210 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 000000002000040c000000001fffff44000000 + 25210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25220 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 000000002000040c000000001fffff44000000 + 25220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8164 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 0000000020000063800000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f90, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h001 } + 25230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h818a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h43, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } +instret:239 PC:0x1ffff0000000000000000000080000168 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2523 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 71 <= 0000000020000065800000001fffff44000000 + 25240 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h818a } + 25240 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 25240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRAM, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h76, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h005, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 00000000200003c8000000001fffff44000000 + 25250 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25250 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 0000000000000004000000001fffff44000000 + 25250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000196 o: 'h0000000080000196 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 25250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:240 PC:0x1ffff000000000000000000008000016c instr:0x0000c119 iType:Br [doCommitNormalInst [0]] 2525 +instret:241 PC:0x1ffff000000000000000000008000016e instr:0x0140006f iType:J [doCommitNormalInst [1]] 2525 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4f <= 00000000200003d4000000001fffff44000000 + 25260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 25260 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:242 PC:0x1ffff0000000000000000000080000182 instr:0xfd043503 iType:Ld [doCommitNormalInst [0]] 2526 +instret:243 PC:0x1ffff0000000000000000000080000186 instr:0xfca43423 iType:St [doCommitNormalInst [1]] 2526 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffef2 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8186 } + 25270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25270 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 25270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8186 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Xor, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 25280 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8186 } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8186 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:244 PC:0x1ffff000000000000000000008000018a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2528 +instret:245 PC:0x1ffff000000000000000000008000018e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2528 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 79 <= 0000000020004443800000001fffff44000000 + 25290 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 25290 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8102 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 25290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:246 PC:0x1ffff0000000000000000000080000192 instr:0xf68080e7 iType:Jr [doCommitNormalInst [0]] 2529 +instret:247 PC:0x1ffff00000000000000000000800000f6 instr:0x00007179 iType:Alu [doCommitNormalInst [1]] 2529 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7f <= 0000000020004400000000001fffff44000000 + 25300 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 0000000000000004000000001fffff44000000 + 25300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 +instret:248 PC:0x1ffff00000000000000000000800000f8 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 2530 +instret:249 PC:0x1ffff00000000000000000000800000fa instr:0x0000f022 iType:St [doCommitNormalInst [1]] 2530 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25310 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80f8 } + 25310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080011000, shiftedBE: tagged DataMemAccess , pcHash: 'h8116 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080011000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8116 } +instret:250 PC:0x1ffff00000000000000000000800000fc instr:0x00001800 iType:Alu [doCommitNormalInst [0]] 2531 +instret:251 PC:0x1ffff00000000000000000000800000fe instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2531 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 25320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8118 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080011000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8116 } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080011000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8116 } + 25320 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } } + 25320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 25320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } +instret:252 PC:0x1ffff0000000000000000000080000102 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2532 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 67 <= 3fffffffffffffffcfff00001fffff44000000 + 25330 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7b <= 0000000004000007800000001fffff44000000 + 25330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffffffffffff o: 'hffffffffffffffff b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 25330 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 25330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + 25330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 25340 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 0000000000000004000000001fffff44000000 + 25340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f8 } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 25340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:253 PC:0x1ffff0000000000000000000080000106 instr:0xfe95055b iType:Cap [doCommitNormalInst [0]] 2534 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80fa } + 25350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8128 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 25350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fa } +instret:254 PC:0x1ffff000000000000000000008000010a instr:0xfea43023 iType:St [doCommitNormalInst [0]] 2535 +instret:255 PC:0x1ffff000000000000000000008000010e instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 2535 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False }, paddr: 'h0000000080011000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 25360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8134 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25360 : [doRespLdForward] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000004000000001fffff44000000 + 25360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fa } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fa } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } +instret:256 PC:0x1ffff0000000000000000000080000112 instr:0xef250593 iType:Alu [doCommitNormalInst [0]] 2536 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 05 <= 3ffffffffffffffbcfff00001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80fe } + 25370 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 25370 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 25370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 25370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } +instret:257 PC:0x1ffff0000000000000000000080000116 instr:0x00006188 iType:Ld [doCommitNormalInst [0]] 2537 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000004000003400000001fffff44000000 + 25380 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000020004404000000001fffff44000000 + 25380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 25380 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 25380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 44 <= 0000000000000004000000001fffff44000000 + 25390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 25390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8140 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25390 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 000000002000040a000000001fffff44000000 + 25390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80fe } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 25390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h810a } + 25400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 25400 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 25400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h810a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7d <= 00000000200003d4000000001fffff44000000 + 25410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 25410 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000020004404000000001fffff44000000 + 25410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h810a } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h810a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 25410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 01 <= 000000004000480e000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8144 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000100012038 o: 'h0000000100012038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 25420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 25430 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 25430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 25430 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 25430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 25440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25440 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000020000065800000001fffff44000000 + 25440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 25450 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 25450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25460 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 00000000200003f0000000001fffff44000000 + 25460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 25480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25500 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 25500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h819a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h819e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25510 : [doRespLdForward] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000020004404000000001fffff44000000 + 25510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 25510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 25520 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25520 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 25520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81b0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 25530 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 000000002000040c000000001fffff44000000 + 25530 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 25530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25540 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 25540 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h81b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25540 : [doRespLdForward] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 56 <= 40000000000000000000ffff1fffff44000000 + 25540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25540 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25550 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 25550 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 25550 : [Ld resp] 'h06; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 25550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25550 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25550 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 0000000000003ff8000000001fffff44000000 + 25560 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25560 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81cc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 25560 : [doRespLdMem] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 000000002000040c000000001fffff44000000 + 25560 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000ffe0 o: 'h000000000000ffe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 25560 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 25560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25560 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 00000000200003c4000000001fffff44000000 +[RFile] wr_ 1: r 55 <= 0000000020000079000000001fffff44000000 + 25570 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 25570 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000004000000001fffff44000000 + 25570 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4a <= 000000002000007b000000001fffff44000000 + 25580 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25580 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h81d0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25580 : [doRespLdForward] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 54 <= 40000000000000000000ffff1fffff44000000 + 25580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 25580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 42 <= 400000002000040c0000ffff1fffff44000000 + 25590 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 25590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 25590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 25590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 25590 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 25590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 25590 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5d <= 0000000000000004000000001fffff44000000 +[RFile] wr_ 1: r 74 <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 25600 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25600 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000007800000001fffff44000000 + 25600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25600 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 25600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25610 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 25610 : [doRespLdForward] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4b <= 40000000000000000000ffff1fffff44000000 + 25610 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25620 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 25620 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001ec o: 'h00000000800001ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 25620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 57 <= 40000000000000000000ffff1ffff800078000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25630 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 0000000000003ff8000000001fffff44000000 + 25630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h0000000000000001e sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 25630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 25630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 25640 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 25640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 25650 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 25650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 25650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 25650 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Xor, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h78, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h05, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu And, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h78, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0d}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Valid 'h05, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f38, check_inclusive: True } }, specBits: 'h000 } + 25770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8118 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080000f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8118 } + 25780 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f38 +After delta: vaddr = 0x80000f38 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25790 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 78 <= 3fffffffffffffffcfff00001fffff44000000 + 25790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f38, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f38,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f38 o: 'h0000000080000f38 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f38, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 25800 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f38, shiftedBE: tagged DataMemAccess , pcHash: 'h8128 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 25800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 25810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + 25810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080000f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8128 } + 25810 : [Ld resp] 'h0a; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 25810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 +instret:258 PC:0x1ffff0000000000000000000080000118 instr:0xfe043603 iType:Ld [doCommitNormalInst [0]] 2581 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 05 <= 0000000000000000000000001fffff44000000 + 25820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 25820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8134 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25820 : [doRespLdMem] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000004000000001fffff44000000 + 25820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7e <= 0000000004000007800000001fffff44000000 + 25830 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 25830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 25830 : [Ld resp] 'h0b; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 25830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 25830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } +instret:259 PC:0x1ffff000000000000000000008000011c instr:0xfff64693 iType:Alu [doCommitNormalInst [0]] 2583 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 40 <= 0000000004000007800000001fffff44000000 + 25840 : [doRespLdMem] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000020004404000000001fffff44000000 + 25840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000001000001e o: 'h000000001000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 25840 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + 25840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:260 PC:0x1ffff0000000000000000000080000120 instr:0x00009536 iType:Alu [doCommitNormalInst [0]] 2584 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000000000004000000001fffff44000000 + 25850 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 25850 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 000000002000040a000000001fffff44000000 + 25850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 25850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:261 PC:0x1ffff0000000000000000000080000122 instr:0x00008d71 iType:Alu [doCommitNormalInst [0]] 2585 +calling cycle + 25860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 25860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 25860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:262 PC:0x1ffff0000000000000000000080000124 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2586 +calling cycle +[RFile] wr_ 1: r 7d <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000f38, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 25870 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8124 } + 25870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8140 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 25870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 25870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 25870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8124 } +calling cycle +[RFile] wr_ 1: r 01 <= 000000004000480e000000001fffff44000000 + 25880 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 25880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8144 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25880 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000004000007800000001fffff44000000 + 25880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000100012038 o: 'h0000000100012038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8124 } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8124 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 25880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } +instret:263 PC:0x1ffff0000000000000000000080000128 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2588 +instret:264 PC:0x1ffff000000000000000000008000012c instr:0xfe85055b iType:Cap [doCommitNormalInst [1]] 2588 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25890 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 25890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 25890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 25890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 25890 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 25890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:265 PC:0x1ffff0000000000000000000080000130 instr:0xfca43823 iType:St [doCommitNormalInst [0]] 2589 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 25900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8130 } + 25900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 25900 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000020000065800000001fffff44000000 + 25900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } +calling cycle + 25910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } +calling cycle + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 25920 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 25930 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8130 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 25930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 25990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 26000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f20 +After delta: vaddr = 0x80000f20 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 26020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8134 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f20, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26030 : [doFinishMem] DTlbResp { resp: <'h0000000080000f20,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f20, check_high: 'h00000000080000f28, check_inclusive: True } }, specBits: 'h000 } + 26030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f20, shiftedBE: tagged DataMemAccess , pcHash: 'h8138 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8134 } + 26030 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f28 +After delta: vaddr = 0x80000f28 + 26030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26040 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0b <= 0000000004000007800000001fffff44000000 + 26040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f28, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 26040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080000f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8138 } + 26040 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 26040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 26040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h77, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f28,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f28 o: 'h0000000080000f28 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f28, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 26050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f28, shiftedBE: tagged DataMemAccess , pcHash: 'h8140 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26050 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 02 <= 0000000000000004000000001fffff44000000 + 26050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 26050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False }, paddr: 'h0000000080000f20, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 26060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h8144 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f20 o: 'h0000000080000f20 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080000f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8140 } + 26060 : [Ld resp] 'h0f; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } } + 26060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } +instret:266 PC:0x1ffff0000000000000000000080000134 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2606 +calling cycle +[RFile] wr_ 0: r 7d <= 00000000200003d4000000001fffff44000000 + 26070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 26070 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h8146 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26070 : [doRespLdMem] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 46 <= 0000000004000007800000001fffff44000000 + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8144 } + 26070 : [Ld resp] 'h10; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } } + 26070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7f, src2: tagged Valid 'h01, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011000 +After delta: vaddr = 0x80011000 + 26070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } +instret:267 PC:0x1ffff0000000000000000000080000138 instr:0xfd043603 iType:Ld [doCommitNormalInst [0]] 2607 +calling cycle +[RFile] wr_ 1: r 01 <= 000000000400000b800000001fffff44000000 + 26080 : [doRespLdMem] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 77 <= 0000000020000065800000001fffff44000000 + 26080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000001000002e o: 'h000000001000002e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8146 } + 26080 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False } } + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 26090 : [doFinishMem] DTlbResp { resp: <'h0000000080011000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011000 o: 'h0000000080011000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011000, check_high: 'h00000000080011008, check_inclusive: True } }, specBits: 'h000 } + 26090 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0a <= 00000000200003f0000000001fffff44000000 +instret:268 PC:0x1ffff000000000000000000008000013c instr:0x00009532 iType:Alu [doCommitNormalInst [0]] 2609 +calling cycle +instret:269 PC:0x1ffff000000000000000000008000013e instr:0x0000e188 iType:St [doCommitNormalInst [0]] 2610 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False }, paddr: 'h0000000080000f28, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[ALU redirect - 0] 'h1ffff0000000000000000000080000196; 'h0; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080011000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h813e } + 26110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080011000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h813e } +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h04, t: 'h08 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080011000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h813e } + 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080011000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h813e } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:270 PC:0x1ffff0000000000000000000080000140 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2613 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0a, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:271 PC:0x1ffff0000000000000000000080000144 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 2614 +calling cycle +instret:272 PC:0x1ffff0000000000000000000080000146 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 2615 +instret:273 PC:0x1ffff0000000000000000000080000148 instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 2615 +calling cycle +instret:274 PC:0x1ffff000000000000000000008000014a instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2616 +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 26200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sub, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000001000001e o: 'h000000001000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 26210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 26220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 26230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h819a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:275 PC:0x1ffff0000000000000000000080000196 instr:0xfca43023 iType:St [doCommitNormalInst [0]] 2623 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8196 } + 26240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h819e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26240 : [doRespLdForward] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 08 <= 0000000004000007800000001fffff44000000 + 26240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 4d <= 40000000000000000000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h819e } + 26250 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } } + 26250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8196 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26260 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26260 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 75 <= 000000002000040c000000001fffff44000000 + 26260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8196 } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8196 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 +instret:276 PC:0x1ffff000000000000000000008000019a instr:0xfc043503 iType:Ld [doCommitNormalInst [0]] 2626 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds CRRL, capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h73, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26270 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81b0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 26270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26270 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffb8, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26280 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 26280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h81b4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26280 : [doRespLdForward] 'h14; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 56 <= 40000000000000000000ffff1fffff44000000 + 26280 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 26280 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } +instret:277 PC:0x1ffff000000000000000000008000019e instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2628 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 26290 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffefee o: 'hffffffff8fffefee b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81b4 } + 26290 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } } + 26290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26290 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + 26290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26300 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 26300 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 51 <= 000000002000040c000000001fffff44000000 + 26300 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:278 PC:0x1ffff00000000000000000000800001a2 instr:0x00008d0d iType:Alu [doCommitNormalInst [0]] 2630 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26310 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 26310 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h81c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 26310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } +instret:279 PC:0x1ffff00000000000000000000800001a4 instr:0xfaa43c23 iType:St [doCommitNormalInst [0]] 2631 +instret:280 PC:0x1ffff00000000000000000000800001a8 instr:0x0210055b iType:Cap [doCommitNormalInst [1]] 2631 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26320 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81a4 } + 26320 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81cc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 26320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c0 } + 26320 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +instret:281 PC:0x1ffff00000000000000000000800001ac instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2632 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 42 <= 400000002000040c0000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 26330 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 26330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h81d0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26330 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 73 <= 0000000000000004000000001fffff44000000 + 26330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81a4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26340 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81ac } + 26340 : [doRespLdForward] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 54 <= 40000000000000000000ffff1fffff44000000 + 26340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 26340 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 26340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffff98, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ac } +instret:282 PC:0x1ffff00000000000000000000800001b0 instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2634 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26350 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26350 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 26350 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000007800000001fffff44000000 + 26350 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ac } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ac } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + 26350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:283 PC:0x1ffff00000000000000000000800001b4 instr:0xfc843583 iType:Ld [doCommitNormalInst [0]] 2635 +instret:284 PC:0x1ffff00000000000000000000800001b8 instr:0x20b5055b iType:Cap [doCommitNormalInst [1]] 2635 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000079000000001fffff44000000 +[RFile] wr_ 1: r 5d <= 0000000000000004000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26360 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 26360 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26360 : [doRespLdForward] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4b <= 400000002000040c0000ffff1fffff44000000 + 26360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffff98, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 26360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } +instret:285 PC:0x1ffff00000000000000000000800001bc instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2636 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 000000002000007b000000001fffff44000000 +[RFile] wr_ 1: r 50 <= 00000000200003c4000000001fffff44000000 + 26370 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81bc } + 26370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001ec o: 'h00000000800001ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 26370 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +instret:286 PC:0x1ffff00000000000000000000800001c0 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2637 +instret:287 PC:0x1ffff00000000000000000000800001c4 instr:0xfe85055b iType:Cap [doCommitNormalInst [1]] 2637 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 40000000000000000000ffff1ffff800078000 + 26380 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 26380 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 26380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h0000000000000001e sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81bc } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 26380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 26380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:288 PC:0x1ffff00000000000000000000800001c8 instr:0xf8a43c23 iType:St [doCommitNormalInst [0]] 2638 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 26390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h81c8 } + 26390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 26390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c8 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + 26400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 26400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c8 } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81c8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 26400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26410 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 26410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffefee o: 'hffffffff8fffefee b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 26410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 26420 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 26420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 26420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26430 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 26430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8218 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 26430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 26430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hc } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26440 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 26440 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26440 : [doRespLdForward] 'h03; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 62 <= 400000002000040c0000ffff1fffff44000000 + 26440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 26440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 26450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26450 : [doRespLdForward] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 26450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 26450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26460 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 26460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h822c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 26460 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 26460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 00000000200003d4000000001fffff44000000 + 26470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 26470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h822e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26470 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 3ffdff00200004020fff00001fffff48000018 + 26470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 7ffdfdc02000040c0000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 26480 : [doRespLdForward] 'h06; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 000000002000007b000000001fffff44000000 + 26480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7f70080001030 o: 'h0007f70080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 26490 : [doRespLdForward] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 00000000200003f0000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 26510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001008 o: 'hfe77fc0080001008 b: 'h0180000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26510 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26600 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26610 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26610 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffff98, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 26620 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26620 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffff98, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f58 +After delta: vaddr = 0x80000f58 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26630 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26630 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81cc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26630 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffff98, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f58, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26630 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26640 : [doFinishMem] DTlbResp { resp: <'h0000000080000f58,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f58 o: 'h0000000080000f58 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f58, check_high: 'h00000000080000f60, check_inclusive: True } }, specBits: 'h000 } + 26640 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000f58, shiftedBE: tagged DataMemAccess , pcHash: 'h81d0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81cc } + 26640 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26640 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26640 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26650 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 54 <= 400000002000040c0000ffff1fffff44000000 + 26650 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080000f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d0 } + 26650 : [Ld resp] 'h07; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } } + 26650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26650 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 26660 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26660 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26660 : [doRespLdMem] 'h07; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 53 <= 0000000000000004000000001fffff44000000 + 26660 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26660 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 55 <= 0000000020000079000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False }, paddr: 'h0000000080000f58, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26670 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 26670 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 26670 : [Ld resp] 'h08; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26670 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 26670 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } +instret:289 PC:0x1ffff00000000000000000000800001cc instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2667 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4a <= 000000002000007b000000001fffff44000000 +[RFile] wr_ 1: r 50 <= 00000000200003c4000000001fffff44000000 + 26680 : [doRespLdMem] 'h08; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4b <= 400000002000040c0000ffff1fffff44000000 + 26680 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001ec o: 'h00000000800001ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 26680 : [Ld resp] 'h09; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 26680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26680 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:290 PC:0x1ffff00000000000000000000800001d0 instr:0xf9843583 iType:Ld [doCommitNormalInst [0]] 2668 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 57 <= 400000002000040c1030ffff1ffff804101030 + 26690 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 26690 : [doRespLdMem] 'h09; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 26690 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001030 o: 'h0000000000000000 b: 'h0000000080001030 t: 'h00000000080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 26690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 74 <= 00000000200003d4000000001fffff44000000 + 26700 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26700 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 26700 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:291 PC:0x1ffff00000000000000000000800001d4 instr:0x10b5055b iType:Cap [doCommitNormalInst [0]] 2670 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26710 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 26710 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001030 o: 'h0000000080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26710 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 26710 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:292 PC:0x1ffff00000000000000000000800001d8 instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2671 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 26720 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81d8 } + 26720 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffefee o: 'hffffffff8fffefee b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26720 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 26720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d8 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26730 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 26730 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d8 } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81d8 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 26730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 26730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26740 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 26740 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8218 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 26740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 26740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hb } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 26750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26750 : [doRespLdForward] 'h0a; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 62 <= 400000002000040c0000ffff1fffff44000000 + 26750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 26750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle + 26760 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 26760 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26760 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 26760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 26760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 26770 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 26770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h822c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 26770 : [Ld resp] 'h0c; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 26770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 26780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 26780 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h822e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 26780 : [doRespLdMem] 'h0c; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 3ffdff00200004020fff00001fffff48000018 + 26780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 70 <= 7ffdfdc02000040c0000ffff1fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26790 : [doRespLdForward] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 000000002000007b000000001fffff44000000 + 26790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7f70080001030 o: 'h0007f70080001030 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 26800 : [doRespLdForward] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 00000000200003f0000000001fffff44000000 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26810 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 26820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001008 o: 'hfe77fc0080001008 b: 'h0180000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26820 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 26920 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffb8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h7d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000024 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 26930 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffb8, regs: PhyRegs { src1: tagged Valid 'h0a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26940 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 26940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81dc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26940 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffb8, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26940 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 55 <= 0000000020000079000000001fffff44000000 + 26950 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f7c, check_inclusive: True } }, specBits: 'h000 } + 26950 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h81e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 26950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 26950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080000f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81dc } + 26950 : [Ld resp] 'h0d; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } } + 26950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26950 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 26950 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 26950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 50 <= 00000000200003c4000000001fffff44000000 +[RFile] wr_ 1: r 4a <= 000000002000007b000000001fffff44000000 + 26960 : [doRespLdMem] 'h0d; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4b <= 400000002000040c1030ffff1ffff804101030 + 26960 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800001ec o: 'h00000000800001ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080000f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81e0 } + 26960 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26960 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h0a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 26960 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 26970 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 26970 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 52 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 26970 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26970 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 26970 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffdc, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 74 <= 00000000200003d4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 26980 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 26980 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001030 o: 'h0000000000000000 b: 'h0000000080001030 t: 'h00000000080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 26980 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c + 26980 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:293 PC:0x1ffff00000000000000000000800001dc instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2698 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged AndPerm , capChecks: CapChecks {rn1 'h0a, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 26990 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 26990 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hffffffff8fffefee o: 'hffffffff8fffefee b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 26990 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f30 +After delta: vaddr = 0x80000f30 + 26990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffdc, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:294 PC:0x1ffff00000000000000000000800001e0 instr:0xfb842583 iType:Ld [doCommitNormalInst [0]] 2699 +instret:295 PC:0x1ffff00000000000000000000800001e4 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2699 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27000 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } + 27000 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f30, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffdc, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f2c +After delta: vaddr = 0x80000f2c +instret:296 PC:0x1ffff00000000000000000000800001e8 instr:0x024080e7 iType:Jr [doCommitNormalInst [0]] 2700 +instret:297 PC:0x1ffff0000000000000000000080000208 instr:0x00007139 iType:Alu [doCommitNormalInst [1]] 2700 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27010 : [doFinishMem] DTlbResp { resp: <'h0000000080000f30,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f30 o: 'h0000000080000f30 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f30, check_high: 'h00000000080000f40, check_inclusive: True } }, specBits: 'h000 } + 27010 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f30, shiftedBE: tagged DataMemAccess , pcHash: 'h8218 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 27010 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffdc, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f2c, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:298 PC:0x1ffff000000000000000000008000020a instr:0x0000fc06 iType:St [doCommitNormalInst [0]] 2701 +instret:299 PC:0x1ffff000000000000000000008000020c instr:0x0000f822 iType:St [doCommitNormalInst [1]] 2701 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27020 : [doFinishMem] DTlbResp { resp: <'h0000000080000f2c,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f2c o: 'h0000000080000f2c b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f2c, check_high: 'h00000000080000f30, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h820a } + 27020 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f2c, shiftedBE: tagged DataMemAccess , pcHash: 'h821c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27020 : [doRespLdForward] 'h0f; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 62 <= 400000002000040c1030ffff1ffff804101030 + 27020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 27020 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820a } +instret:300 PC:0x1ffff000000000000000000008000020e instr:0x00000080 iType:Alu [doCommitNormalInst [0]] 2702 +instret:301 PC:0x1ffff0000000000000000000080000210 instr:0xfea44023 iType:St [doCommitNormalInst [1]] 2702 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'ha } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False }, paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27030 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 3fffffffe3fffbfb8fff00001fffff44000000 + 27030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820a } + 27030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27030 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 27030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:302 PC:0x1ffff0000000000000000000080000214 instr:0xfcb42e23 iType:St [doCommitNormalInst [0]] 2703 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27040 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h820c } + 27040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27040 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 27040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } +instret:303 PC:0x1ffff0000000000000000000080000218 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2704 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27050 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 27050 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h822c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 27050 : [Ld resp] 'h11; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 27050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Valid 'h70, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 27050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } +instret:304 PC:0x1ffff000000000000000000008000021c instr:0xfdc42583 iType:Ld [doCommitNormalInst [0]] 2705 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6c <= 00000000200003d4000000001fffff44000000 +[RFile] wr_ 1: r 70 <= 7ffdfdc02000040c1030ffff1ffff804101030 + 27060 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 27060 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h822e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27060 : [doRespLdMem] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 68 <= 3ffdff00200004020fff00001fffff48000018 + 27060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7f70080001030 o: 'h0000000000000000 b: 'hfff7f70080001030 t: 'h0fff7f70080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 27060 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27070 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 27070 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 000000002000007b000000001fffff44000000 + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h820c } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:305 PC:0x1ffff0000000000000000000080000220 instr:0x1ab5055b iType:Cap [doCommitNormalInst [0]] 2707 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f30, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8210 } + 27080 : [doRespLdForward] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 00000000200003f0000000001fffff44000000 + 27080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8210 } +instret:306 PC:0x1ffff0000000000000000000080000224 instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2708 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h9 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8210 } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8210 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 27090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 27090 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f2c, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8214 } + 27100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001008 o: 'hfe77fc0080001008 b: 'h0180000000000000 t: 'h00000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27100 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 27100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8214 } +calling cycle +calling cycle + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8214 } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f2c, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8214 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8224 } + 27130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8224 } +calling cycle + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8224 } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8224 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h74, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f10 +After delta: vaddr = 0x80000f10 + 27200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f10, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f48 +After delta: vaddr = 0x80000f48 + 27210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f10,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f10, check_high: 'h00000000080000f20, check_inclusive: True } }, specBits: 'h000 } + 27220 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f10, shiftedBE: tagged DataMemAccess , pcHash: 'h8228 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f48, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f40 +After delta: vaddr = 0x80000f40 + 27220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } +calling cycle + 27230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f48,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f48 o: 'h0000000080000f48 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f48, check_high: 'h00000000080000f50, check_inclusive: True } }, specBits: 'h000 } + 27230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080000f48, shiftedBE: tagged DataMemAccess , pcHash: 'h822c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f10 o: 'h0000000080000f10 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f40, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080000f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8228 } + 27230 : [Ld resp] 'h13; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } } + 27230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } +calling cycle +[RFile] wr_ 1: r 6c <= 00000000200003d4000000001fffff44000000 + 27240 : [doFinishMem] DTlbResp { resp: <'h0000000080000f40,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f40 o: 'h0000000080000f40 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f40, check_high: 'h00000000080000f48, check_inclusive: True } }, specBits: 'h000 } + 27240 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f40, shiftedBE: tagged DataMemAccess , pcHash: 'h822e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27240 : [doRespLdMem] 'h13; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 68 <= 7ffdfdc02000040c1030ffff1ffff804101030 + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080000f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822c } + 27240 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } } + 27240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822e } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False }, paddr: 'h0000000080000f10, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27250 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 43 <= 000000002000007b000000001fffff44000000 + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822e } + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080000f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h822e } + 27250 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 27250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000080000f48, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27260 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 00000000200003f0000000001fffff44000000 +instret:307 PC:0x1ffff0000000000000000000080000228 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2726 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f40, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:308 PC:0x1ffff000000000000000000008000022c instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 2727 +calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800001ec; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:309 PC:0x1ffff000000000000000000008000022e instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 2728 +instret:310 PC:0x1ffff0000000000000000000080000230 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 2728 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:311 PC:0x1ffff0000000000000000000080000232 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2730 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffa0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h68, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + 27370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffa0, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + 27380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffa0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7f70080001030 o: 'h0000000000000000 b: 'hfff7f70080001030 t: 'h0fff7f70080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 27380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffa0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f60 +After delta: vaddr = 0x80000f60 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27390 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 27390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffa0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f60, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27390 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27400 : [doFinishMem] DTlbResp { resp: <'h0000000080000f60,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f60, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 27400 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f60, shiftedBE: tagged DataMemAccess , pcHash: 'h81f0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 27400 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 27400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:312 PC:0x1ffff00000000000000000000800001ec instr:0xfaa44023 iType:St [doCommitNormalInst [0]] 2740 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81ec } + 27410 : [doRespLdForward] 'h16; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 5f <= 7ffdfdc02000040c1030ffff1ffff804101030 + 27410 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ec } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080000f60, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27420 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 27420 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h81fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ec } + 27420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080000f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81ec } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 27420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 27420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } +calling cycle + 27430 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8200 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7f70080001030 o: 'h0000000000000000 b: 'hfff7f70080001030 t: 'h0fff7f70080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 27430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 27430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 27430 : [Ld resp] 'h17; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 27430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } +instret:313 PC:0x1ffff00000000000000000000800001f0 instr:0xfa04250f iType:Ld [doCommitNormalInst [0]] 2743 +calling cycle +[RFile] wr_ 1: r 67 <= 00000000200003f0000000001fffff44000000 + 27440 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 27440 : [doRespLdMem] 'h17; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 66 <= 7ffdff00200004021008ffff1ffff804099008 + 27440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 27440 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle + 27450 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 27450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8202 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27450 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 000000002000001e800000001fffff44000000 + 27450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } +instret:314 PC:0x1ffff00000000000000000000800001f4 instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2745 +instret:315 PC:0x1ffff00000000000000000000800001f8 instr:0x0040006f iType:J [doCommitNormalInst [1]] 2745 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Valid St } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h81f4 } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 27460 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f4 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27470 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000400000000001fffff44000000 + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f4 } + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81f4 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 27470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27560 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27570 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 27570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000068, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000070 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27580 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000068, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 27580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000060, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27590 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 27590 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h81fc } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000068, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000060, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 27590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } +calling cycle + 27600 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 27600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8200 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000060, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f50 o: 'h0000000080000f50 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080000fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h81fc } + 27600 : [Ld resp] 'h01; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } +calling cycle +[RFile] wr_ 1: r 67 <= 00000000200003f0000000001fffff44000000 + 27610 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 27610 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8202 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27610 : [doRespLdMem] 'h01; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 66 <= 7ffdfdc02000040c1030ffff1ffff804101030 + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8200 } + 27610 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } } + 27610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27620 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 76 <= 000000002000001e800000001fffff44000000 + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8202 } + 27620 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } } + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27630 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7a <= 0000000020000400000000001fffff44000000 +instret:316 PC:0x1ffff00000000000000000000800001fc instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2763 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +instret:317 PC:0x1ffff0000000000000000000080000200 instr:0x000070a6 iType:Ld [doCommitNormalInst [0]] 2764 +calling cycle +[ALU redirect - 1] 'h1ffff000000000000000000008000007a; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } +instret:318 PC:0x1ffff0000000000000000000080000202 instr:0x00007406 iType:Ld [doCommitNormalInst [0]] 2765 +instret:319 PC:0x1ffff0000000000000000000080000204 instr:0x00006165 iType:Alu [doCommitNormalInst [1]] 2765 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:320 PC:0x1ffff0000000000000000000080000206 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 2767 +calling cycle +calling cycle +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27730 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27740 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Valid 'h66, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 27740 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27750 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7f70080001030 o: 'h0000000000000000 b: 'hfff7f70080001030 t: 'h0fff7f70080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 27750 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27760 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 27760 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000043 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6a <= 0000000000000000400000001fffff44000000 + 27770 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 27770 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h807e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 27770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807e } +instret:321 PC:0x1ffff000000000000000000008000007a instr:0xfca44023 iType:St [doCommitNormalInst [0]] 2777 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000042 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h807a } + 27780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807e } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807e } + 27780 : [Ld resp] 'h04; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27790 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 27790 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h8088 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27790 : [doRespLdMem] 'h04; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4e <= 7ffdff00200004021008ffff1ffff804099008 + 27790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } + 27790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 27790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 27790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8088 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 40 <= 0000000000000010c00000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8088 } + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8088 } + 27800 : [Ld resp] 'h05; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 27800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } +Decoded delta from register = 33550328 +Before delta: vaddr = 0x80001008 +After delta: vaddr = 0x82000000 + 27800 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h056 }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h6a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 44 <= 0000000000000010800000001fffff44000000 + 27810 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h000 } + 27810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h8098 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27810 : [doRespLdMem] 'h05; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7e <= 7ffdff00200004021008ffff1ffff804099008 + 27810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000082000000 o: 'h0000000000000000 b: 'h0000000082001008 t: 'h00000000082001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000082000000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27810 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 + 27810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8098 } +instret:322 PC:0x1ffff000000000000000000008000007e instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2781 +instret:323 PC:0x1ffff0000000000000000000080000082 instr:0x00004585 iType:Alu [doCommitNormalInst [1]] 2781 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27820 : [doFinishMem] DTlbResp { resp: <'h0000000082000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000082000000 o: 'h0000000000000000 b: 'h0000000082001008 t: 'h00000000082001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'hfff7fc0080001008, authority_top: 'h0fff7fc0080001026, authority_idx: 'h0a, check_low: 'h0000000082000000, check_high: 'h00000000082000004, check_inclusive: True } }, specBits: 'h000 } + 27820 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8098 } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8098 } + 27820 : [Ld resp] 'h06; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27820 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27830 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h000 } + 27830 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h80a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27830 : [doRespLdMem] 'h06; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 47 <= 7ffdfdc02000040c1030ffff1ffff804101030 + 27830 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Valid 'h40, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } +Decoded delta from register = 33550328 +Before delta: vaddr = 0x8000100c +After delta: vaddr = 0x82000004 + 27830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } +instret:324 PC:0x1ffff0000000000000000000080000084 instr:0xf8b5055b iType:St [doCommitNormalInst [0]] 2783 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 7c <= 7ffdff0020000403100cffff1ffff804099008 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000082000000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8084 } + 27840 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'hfff7fc008000100c o: 'h0000000000000004 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000043 o: 'h0000000000000043 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000082000004 o: 'h0000000000000004 b: 'h0000000082001008 t: 'h00000000082001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000082000004, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } + 27840 : [Ld resp] 'h07; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h44, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } +Decoded delta from register = 33550318 +Before delta: vaddr = 0x80001030 +After delta: vaddr = 0x8200001e + 27840 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffc0, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 27840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000042 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27850 : [doFinishMem] DTlbResp { resp: <'h0000000082000004,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000082000004 o: 'h0000000000000004 b: 'h0000000082001008 t: 'h00000000082001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'hfff7fc0080001008, authority_top: 'h0fff7fc0080001026, authority_idx: 'h0c, check_low: 'h0000000082000004, check_high: 'h00000000082000008, check_inclusive: True } }, specBits: 'h000 } + 27850 : [doRespLdMem] 'h07; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 0b <= 7ffdff00200004021008ffff1ffff804099008 + 27850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'hfff7f70080001030 o: 'h0000000000000000 b: 'hfff7f70080001030 t: 'h0fff7f70080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000042 o: 'h0000000000000042 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008200001e o: 'h0000000000000000 b: 'h0000000082001030 t: 'h00000000082001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008200001e, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } + 27850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 27850 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffc0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h003 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fc0 +After delta: vaddr = 0x80000fc0 + 27850 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:325 PC:0x1ffff0000000000000000000080000088 instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2785 +instret:326 PC:0x1ffff000000000000000000008000008c instr:0x0045165b iType:Cap [doCommitNormalInst [1]] 2785 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h066 }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 27860 : [doFinishMem] DTlbResp { resp: <'h000000008200001e,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008200001e o: 'h0000000000000000 b: 'h0000000082001030 t: 'h00000000082001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'hfff7f70080001030, authority_top: 'h0fff7f70080001040, authority_idx: 'h0c, check_low: 'h000000008200001e, check_high: 'h0000000008200001f, check_inclusive: True } }, specBits: 'h000 } + 27860 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffc0, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h00, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fc0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 27860 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 } +Decoded delta from register = 33550328 +Before delta: vaddr = 0x80001008 +After delta: vaddr = 0x82000000 +instret:327 PC:0x1ffff0000000000000000000080000090 instr:0x04300513 iType:Alu [doCommitNormalInst [0]] 2786 +instret:328 PC:0x1ffff0000000000000000000080000094 instr:0xf8a6055b iType:St [doCommitNormalInst [1]] 2786 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000010 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27870 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000082000000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27870 : [doFinishMem] DTlbResp { resp: <'h0000000080000fc0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fc0, check_high: 'h00000000080000fd0, check_inclusive: True } }, specBits: 'h001 } + 27870 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080000fc0, shiftedBE: tagged DataMemAccess , pcHash: 'h80c0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27870 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000082000000 o: 'h0000000000000000 b: 'h0000000082001008 t: 'h00000000082001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000082000000, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } +calling cycle +[RFile] wr_ 0: r 69 <= 0000000000000010800000001fffff44000000 + 27880 : [doFinishMem] DTlbResp { resp: <'h0000000082000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000082000000 o: 'h0000000000000000 b: 'h0000000082001008 t: 'h00000000082001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'hfff7fc0080001008, authority_top: 'h0fff7fc0080001026, authority_idx: 'h0a, check_low: 'h0000000082000000, check_high: 'h00000000082000004, check_inclusive: True } }, specBits: 'h000 } + 27880 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000082000000, shiftedBE: tagged DataMemAccess , pcHash: 'h80a8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 27880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080000fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 27880 : [Ld resp] 'h09; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } } + 27880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:329 PC:0x1ffff0000000000000000000080000098 instr:0xfc04260f iType:Ld [doCommitNormalInst [0]] 2788 +instret:330 PC:0x1ffff000000000000000000008000009c instr:0x04200513 iType:Alu [doCommitNormalInst [1]] 2788 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h07, instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27890 : [doRespLdMem] 'h09; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 4f <= 7ffdfdc02000040c1030ffff1ffff804101030 + 27890 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:331 PC:0x1ffff00000000000000000000800000a0 instr:0xf8a6045b iType:St [doCommitNormalInst [0]] 2789 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 27900 : [doRespLdForward] 'h08; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 49 <= 0000000000000000400000001fffff44000000 + 27900 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h001 } +Decoded delta from register = 33550318 +Before delta: vaddr = 0x80001030 +After delta: vaddr = 0x8200001e + 27900 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h007, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:332 PC:0x1ffff00000000000000000000800000a4 instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2790 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000150 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h08, instTag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False }, paddr: 'h0000000082000000, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27910 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'hfff7f70080001030 o: 'h0000000000000000 b: 'hfff7f70080001030 t: 'h0fff7f70080001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h000000008200001e o: 'h0000000000000000 b: 'h0000000082001030 t: 'h00000000082001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h000000008200001e, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 27910 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h7a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h005 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fd0 +After delta: vaddr = 0x80000fd0 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h09, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False }, paddr: 'h0000000080000fc0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } + 27920 : [doFinishMem] DTlbResp { resp: <'h000000008200001e,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h000000008200001e o: 'h0000000000000000 b: 'h0000000082001030 t: 'h00000000082001040 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'hfff7f70080001030, authority_top: 'h0fff7f70080001040, authority_idx: 'h0a, check_low: 'h000000008200001e, check_high: 'h0000000008200001f, check_inclusive: True } }, specBits: 'h001 } + 27920 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h000000008200001e, shiftedBE: tagged DataMemAccess , pcHash: 'h80c4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 27920 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h005 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fd0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc +instret:333 PC:0x1ffff00000000000000000000800000a8 instr:0xfaa5055b iType:Ld [doCommitNormalInst [0]] 2792 +calling cycle + 27930 : [doFinishMem] DTlbResp { resp: <'h0000000080000fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fd0 o: 'h0000000080000fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fd0, check_high: 'h00000000080000fe0, check_inclusive: True } }, specBits: 'h005 } + 27930 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080000fd0, shiftedBE: tagged DataMemAccess , pcHash: 'h80e0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 27930 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5e <= 0000000000000010800000001fffff44000000 + 27930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e0 } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000039000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0a, instTag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: True, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h000000008200001e, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e0 } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080000fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80e0 } + 27940 : [Ld resp] 'h0b; TaggedData { tag: True, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:334 PC:0x1ffff00000000000000000000800000ac instr:0x00b51463 iType:Br [doCommitNormalInst [0]] 2794 +instret:335 PC:0x1ffff00000000000000000000800000b0 instr:0x0100006f iType:J [doCommitNormalInst [1]] 2794 +calling cycle +[RFile] wr_ 1: r 45 <= 000000002000003b000000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000234; 'h3; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } + 27950 : [doRespLdMem] 'h0b; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 7f <= 7ffdff00200004021008ffff1ffff804099008 +instret:336 PC:0x1ffff00000000000000000000800000c0 instr:0xfc04250f iType:Ld [doCommitNormalInst [0]] 2795 +instret:337 PC:0x1ffff00000000000000000000800000c4 instr:0xfac5055b iType:Ld [doCommitNormalInst [1]] 2795 +calling cycle +[ROB incorrectSpec] 'h3 ; InstTag { way: 'h1, ptr: 'h0d, t: 'h1b } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h0 ; ; +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0b, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False }, paddr: 'h0000000080000fd0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +instret:338 PC:0x1ffff00000000000000000000800000c8 instr:0x04200593 iType:Alu [doCommitNormalInst [0]] 2797 +calling cycle +instret:339 PC:0x1ffff00000000000000000000800000cc instr:0x00b51463 iType:Br [doCommitNormalInst [0]] 2798 +instret:340 PC:0x1ffff00000000000000000000800000d0 instr:0x0100006f iType:J [doCommitNormalInst [1]] 2798 +calling cycle +instret:341 PC:0x1ffff00000000000000000000800000e0 instr:0xfd04250f iType:Ld [doCommitNormalInst [0]] 2799 +instret:342 PC:0x1ffff00000000000000000000800000e4 instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2799 +calling cycle +instret:343 PC:0x1ffff00000000000000000000800000e8 instr:0x150080e7 iType:Jr [doCommitNormalInst [0]] 2800 +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h75, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28030 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28040 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 28040 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h59, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 60 <= 00000000200003e4000000001fffff44000000 + 28050 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h00000000800000ec o: 'h00000000800000ec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28050 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 + 28050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 75 <= 00000000200003f0000000001fffff44000000 + 28060 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 28060 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 28060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:344 PC:0x1ffff0000000000000000000080000234 instr:0x00007179 iType:Alu [doCommitNormalInst [0]] 2806 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28070 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 28070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'hfff7fc0080001008 o: 'h0000000000000000 b: 'hfff7fc0080001008 t: 'h0fff7fc0080001026 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: True, capStore: True, potentialCapLoad: True } +L1 TLB inc + 28070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0c, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fa0 +After delta: vaddr = 0x80000fa0 + 28070 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:345 PC:0x1ffff0000000000000000000080000236 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 2807 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 28080 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 28080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0c, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fa0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 28080 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0d, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:346 PC:0x1ffff0000000000000000000080000238 instr:0x0000f022 iType:St [doCommitNormalInst [0]] 2808 +instret:347 PC:0x1ffff000000000000000000008000023a instr:0x00001800 iType:Alu [doCommitNormalInst [1]] 2808 +calling cycle + 28090 : [doFinishMem] DTlbResp { resp: <'h0000000080000fa0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0c, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fa0 o: 'h0000000080000fa0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fa0, check_high: 'h00000000080000fb0, check_inclusive: True } }, specBits: 'h000 } + 28090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0c, paddr: 'h0000000080000fa0, shiftedBE: tagged DataMemAccess , pcHash: 'h8240 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, data: TaggedData { tag: True, data: } } + 28090 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0d, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:348 PC:0x1ffff000000000000000000008000023c instr:0xfea44023 iType:St [doCommitNormalInst [0]] 2809 +calling cycle +[RFile] wr_ 1: r 5d <= 0000000020000093800000001fffff44000000 + 28100 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, ldstq_tag: tagged Ld 'h0d, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 28100 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0d, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 28100 : [doRespLdForward] 'h0c; TaggedData { tag: True, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: } } +[RFile] wr_ 3: r 59 <= 7ffdff00200004021008ffff1ffff804099008 + 28100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Geu, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0b, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h155 }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0c, instTag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: True, killed: tagged Invalid } +[RFile] wr_ 1: r 51 <= 0000000020000095800000001fffff44000000 +[ALU redirect - 1] 'h1ffff0000000000000000000080000462; 'h0; InstTag { way: 'h0, ptr: 'h13, t: 'h26 } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 28110 : [Ld resp] 'h0d; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 28110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle - 30080 : [doFinishMem] DTlbResp { resp: <'h00000000800020d8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h00000000800020d8 o: 'h00000000800020d8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h00000000800020d8, check_high: 'h000000000800020e0, check_inclusive: True } }, specBits: 'h000 } -instret:499 PC:0x1ffff00000000000000000000800011b0 instr:0x000095aa iType:Alu [doCommitNormalInst [0]] 3008 -instret:500 PC:0x1ffff00000000000000000000800011b2 instr:0x3ff00513 iType:Alu [doCommitNormalInst [1]] 3008 +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h13, t: 'h26 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h1 ; ; calling cycle -instret:501 PC:0x1ffff00000000000000000000800011b6 instr:0x00001552 iType:Alu [doCommitNormalInst [0]] 3009 -instret:502 PC:0x1ffff00000000000000000000800011b8 instr:0x0000e188 iType:St [doCommitNormalInst [1]] 3009 + 28130 : [doRespLdMem] 'h0d; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 0000000000000004000000001fffff44000000 + 28130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Valid 'h42, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 +instret:349 PC:0x1ffff0000000000000000000080000240 instr:0xfe04250f iType:Ld [doCommitNormalInst [0]] 2813 calling cycle -[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h00000000800020d8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h91b8 } - 30100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91b8 } -instret:503 PC:0x1ffff00000000000000000000800011ba instr:0x00000517 iType:Auipc [doCommitNormalInst [0]] 3010 +[RFile] wr_ 0: r 42 <= 3ffdff00200004020fff00001fffff44000000 + 28140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001008 o: 'hfff7fc0080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc calling cycle - 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } - 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91b8 } - 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit - 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h91b8 } -[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } - 30110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28150 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } +instret:350 PC:0x1ffff0000000000000000000080000244 instr:0x0000852a iType:Alu [doCommitNormalInst [0]] 2815 calling cycle +instret:351 PC:0x1ffff0000000000000000000080000246 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2816 calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0d, instTag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Valid St } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 28190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 28200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 28200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle +[RFile] wr_ 1: r 54 <= 00000000200003d8000000001fffff44000000 + 28210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000256 o: 'h0000000080000256 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 28210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle +[RFile] wr_ 1: r 53 <= 00000000200003e4000000001fffff44000000 + 28220 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 28220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 28220 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h23e }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 28230 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 28230 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000010 o: 'h0000000000000010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 28230 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 28230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle calling cycle @@ -10568,17 +9879,13 @@ calling cycle calling cycle calling cycle calling cycle - [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000005c6 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle calling cycle calling cycle calling cycle -[RFile] wr_ 1: r 73 <= 00000000200005e0000000001fffff44000000 calling cycle -instret:504 PC:0x1ffff00000000000000000000800011be instr:0x5c650513 iType:Alu [doCommitNormalInst [0]] 3055 calling cycle calling cycle -instret:505 PC:0x1ffff00000000000000000000800011c2 instr:0x0000210c iType:Ld [doCommitTrap] 3057 calling cycle calling cycle calling cycle @@ -10588,7 +9895,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3066 calling cycle calling cycle calling cycle @@ -10598,7 +9904,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3075 calling cycle calling cycle calling cycle @@ -10608,7 +9913,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3084 calling cycle calling cycle calling cycle @@ -10618,7 +9922,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3093 calling cycle calling cycle calling cycle @@ -10628,7 +9931,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3102 calling cycle calling cycle calling cycle @@ -10637,28 +9939,79 @@ calling cycle calling cycle calling cycle calling cycle + 29140 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000082000000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } calling cycle -instret:511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3111 + 29150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000041000, cs: M, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29150 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 29150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000082000004, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8094 } + 29160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000082000004, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8094 } calling cycle + 29170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000041000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000082000004, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8094 } + 29170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000082000004, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8094 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h000000008200001e, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 } + 29180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h000000008200001e, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } calling cycle + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000041000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h000000008200001e, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h000000008200001e, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8236 } + 29200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } calling cycle + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8236 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8238 } + 29220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } calling cycle + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8238 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -instret:512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3120 +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000fa0, isMMIO: False, shiftedBE: , stData: TaggedData { tag: True, data: }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h823c } + 29240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h823c } calling cycle + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h823c } + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080000fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h823c } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: True, data: } } + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8246 } + 29260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8246 } calling cycle + 29270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8246 } + 29270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080000f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8246 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle calling cycle calling cycle calling cycle calling cycle calling cycle -instret:513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3129 calling cycle calling cycle calling cycle @@ -10668,7 +10021,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3138 calling cycle calling cycle calling cycle @@ -10678,7 +10030,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3147 calling cycle calling cycle calling cycle @@ -10688,7 +10039,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3156 calling cycle calling cycle calling cycle @@ -10698,37 +10048,257 @@ calling cycle calling cycle calling cycle calling cycle -instret:517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3165 calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 29720 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000214 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 29730 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h75, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f98 +After delta: vaddr = 0x80000f98 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle + 29740 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f98, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle +[RFile] wr_ 1: r 5d <= 0000000020000093800000001fffff44000000 + 29750 : [doFinishMem] DTlbResp { resp: <'h0000000080000f98,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h0e, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f98 o: 'h0000000080000f98 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f98, check_high: 'h00000000080000fa0, check_inclusive: True } }, specBits: 'h000 } + 29750 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0e, paddr: 'h0000000080000f98, shiftedBE: tagged DataMemAccess , pcHash: 'h824a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29750 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000028, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle +[RFile] wr_ 1: r 51 <= 0000000020000095800000001fffff44000000 + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080000f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h824a } + 29760 : [Ld resp] 'h0e; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } } + 29760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29760 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 29760 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000020, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle +[RFile] wr_ 0: r 54 <= 00000000200003d8000000001fffff44000000 + 29770 : [doRespLdMem] 'h0e; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 58 <= 3ffdff00200004020fff00001fffff44000000 + 29770 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000256 o: 'h0000000080000256 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29770 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h75, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 29770 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe8, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } calling cycle -instret:518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3174 +[RFile] wr_ 0: r 53 <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0e, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080000f98, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29780 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 29780 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29780 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 29780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Eq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h23e }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h41, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 29790 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'hd, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 29790 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001008 o: 'hfff7fc0080001008 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 + 29790 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe8, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:352 PC:0x1ffff000000000000000000008000024a instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 2979 +instret:353 PC:0x1ffff000000000000000000008000024e instr:0x00000097 iType:Auipc [doCommitNormalInst [1]] 2979 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29800 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 29800 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29800 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f78 +After delta: vaddr = 0x80000f78 +instret:354 PC:0x1ffff0000000000000000000080000252 instr:0x214080e7 iType:Jr [doCommitNormalInst [0]] 2980 +instret:355 PC:0x1ffff0000000000000000000080000462 instr:0x00007179 iType:Alu [doCommitNormalInst [1]] 2980 +calling cycle + 29810 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, ldstq_tag: tagged Ld 'h0f, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } + 29810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0f, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h846e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29810 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe8, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f78, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:356 PC:0x1ffff0000000000000000000080000464 instr:0x0000f406 iType:St [doCommitNormalInst [0]] 2981 +instret:357 PC:0x1ffff0000000000000000000080000466 instr:0x0000f022 iType:St [doCommitNormalInst [1]] 2981 +calling cycle + 29820 : [doFinishMem] DTlbResp { resp: <'h0000000080000f78,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, ldstq_tag: tagged Ld 'h10, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f78 o: 'h0000000080000f78 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f78, check_high: 'h00000000080000f80, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8464 } + 29820 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h10, paddr: 'h0000000080000f78, shiftedBE: tagged DataMemAccess , pcHash: 'h8478 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, data: TaggedData { tag: False, data: } } + 29820 : [doRespLdForward] 'h0f; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 55 <= 3ffdff00200004020fff00001fffff44000000 + 29820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8464 } +instret:358 PC:0x1ffff0000000000000000000080000468 instr:0x00001800 iType:Alu [doCommitNormalInst [0]] 2982 +instret:359 PC:0x1ffff000000000000000000008000046a instr:0xfea43423 iType:St [doCommitNormalInst [1]] 2982 +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h0f, instTag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 29830 : [doRespLdForward] 'h10; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 41 <= 3ffdff00200004020fff00001fffff44000000 + 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8464 } + 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8464 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29830 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd8, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffb86 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00011000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8466 } + 29840 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h7d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 29840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8466 } +instret:360 PC:0x1ffff000000000000000000008000046e instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2984 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 7d <= 3ffdff00200004000fff00001fffff44000000 + 29850 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001000 o: 'hfff7fc0080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8466 } + 29850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080000f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8466 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 29860 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h846a } + 29860 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 29860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846a } +instret:361 PC:0x1ffff0000000000000000000080000472 instr:0x00001561 iType:Alu [doCommitNormalInst [0]] 2986 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000006 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: False, localTaken: False, pcIndex: 'h250 }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h003, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 6b <= 0000000020004522800000001fffff44000000 + 29870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846a } + 29870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080000f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h846a } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29870 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 29870 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h002, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:362 PC:0x1ffff0000000000000000000080000474 instr:0xfca43c23 iType:St [doCommitNormalInst [0]] 2987 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000fa }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 4b <= 0000000020004404000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h10, instTag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False }, paddr: 'h0000000080000f78, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8474 } + 29880 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29880 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h11, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h002 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 29880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8474 } calling cycle + 29890 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 29890 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h11, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8474 } + 29890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8474 } +[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:363 PC:0x1ffff0000000000000000000080000478 instr:0xfe843503 iType:Ld [doCommitNormalInst [0]] 2989 +instret:364 PC:0x1ffff000000000000000000008000047c instr:0x0000c119 iType:Br [doCommitNormalInst [1]] 2989 calling cycle + 29900 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h11, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 29900 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h11, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h849a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, data: TaggedData { tag: False, data: } } +instret:365 PC:0x1ffff000000000000000000008000047e instr:0x00c0006f iType:J [doCommitNormalInst [0]] 2990 +instret:366 PC:0x1ffff000000000000000000008000048a instr:0x00011517 iType:Auipc [doCommitNormalInst [1]] 2990 calling cycle + 29910 : [doRespLdForward] 'h11; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6d <= 0000000020004404000000001fffff44000000 + 29910 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:367 PC:0x1ffff000000000000000000008000048e instr:0xb8650513 iType:Alu [doCommitNormalInst [0]] 2991 +instret:368 PC:0x1ffff0000000000000000000080000492 instr:0xfea43023 iType:St [doCommitNormalInst [1]] 2991 calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h11, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8492 } + 29920 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011010 +After delta: vaddr = 0x80011010 + 29920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8492 } +instret:369 PC:0x1ffff0000000000000000000080000496 instr:0x0040006f iType:J [doCommitNormalInst [0]] 2992 calling cycle + 29930 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, rVal1: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011010, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8492 } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080000f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8492 } +[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 29930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:370 PC:0x1ffff000000000000000000008000049a instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 2993 calling cycle + 29940 : [doFinishMem] DTlbResp { resp: <'h0000000080011010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged Ld 'h12, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011010, check_high: 'h00000000080011018, check_inclusive: True } }, specBits: 'h000 } + 29940 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h12, paddr: 'h0000000080011010, shiftedBE: tagged DataMemAccess , pcHash: 'h849e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 29940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h849e } calling cycle + 29950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h849e } + 29950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h849e } + 29950 : [Ld resp] 'h12; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } } + 29950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid calling cycle -instret:519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3183 + 29960 : [doRespLdMem] 'h12; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 70 <= 0000000000000000000000001fffff44000000 calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h12, instTag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False }, paddr: 'h0000000080011010, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } calling cycle +instret:371 PC:0x1ffff000000000000000000008000049e instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 2998 calling cycle calling cycle +instret:372 PC:0x1ffff00000000000000000000800004a0 instr:0x0000e119 iType:Br [doCommitNormalInst [0]] 3000 +instret:373 PC:0x1ffff00000000000000000000800004a2 instr:0x0fa0006f iType:J [doCommitNormalInst [1]] 3000 calling cycle calling cycle calling cycle calling cycle calling cycle -instret:520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3192 calling cycle calling cycle calling cycle @@ -10738,7 +10308,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3201 calling cycle calling cycle calling cycle @@ -10748,7 +10317,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3210 calling cycle calling cycle calling cycle @@ -10758,7 +10326,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3219 calling cycle calling cycle calling cycle @@ -10768,27 +10335,228 @@ calling cycle calling cycle calling cycle calling cycle -instret:524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3228 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 30420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle + 30430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 30440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle + 30450 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged Ld 'h13, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 30450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h13, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h859c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 30450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h859c } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 30460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h859c } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h859c } + 30460 : [Ld resp] 'h13; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } } + 30460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd8, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 30470 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h15, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 30470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h15, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h85a2 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30470 : [doRespLdMem] 'h13; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 50 <= 0000000020004404000000001fffff44000000 + 30470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd8, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f68 +After delta: vaddr = 0x80000f68 + 30470 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a2 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000004 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } } calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h13, instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30480 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd8, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h18, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f68, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a2 } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a2 } + 30480 : [Ld resp] 'h15; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } } + 30480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30480 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011010 +After delta: vaddr = 0x80011010 + 30480 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30490 : [doFinishMem] DTlbResp { resp: <'h0000000080000f68,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h16, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f68 o: 'h0000000080000f68 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f68, check_high: 'h00000000080000f70, check_inclusive: True } }, specBits: 'h000 } + 30490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h16, paddr: 'h0000000080000f68, shiftedBE: tagged DataMemAccess , pcHash: 'h85a8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30490 : [doRespLdMem] 'h15; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6f <= 3ffdff00200004000fff00001fffff44000000 + 30490 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, rVal1: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0a, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011010, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30490 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h17, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f70 +After delta: vaddr = 0x80000f70 + 30490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a8 } +instret:374 PC:0x1ffff000000000000000000008000059c instr:0xfe043503 iType:Ld [doCommitNormalInst [0]] 3049 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h8 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 30500 : [doFinishMem] DTlbResp { resp: <'h0000000080011010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, ldstq_tag: tagged Ld 'h14, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011010, check_high: 'h00000000080011018, check_inclusive: True } }, specBits: 'h000 } + 30500 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h14, paddr: 'h0000000080011010, shiftedBE: tagged DataMemAccess , pcHash: 'h85a0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30500 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h17, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f70, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a8 } + 30500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080000f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a8 } + 30500 : [Ld resp] 'h16; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } } + 30500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f88 +After delta: vaddr = 0x80000f88 + 30500 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a0 } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 30510 : [doFinishMem] DTlbResp { resp: <'h0000000080000f70,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged Ld 'h17, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f70 o: 'h0000000080000f70 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f70, check_high: 'h00000000080000f78, check_inclusive: True } }, specBits: 'h000 } + 30510 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h17, paddr: 'h0000000080000f70, shiftedBE: tagged DataMemAccess , pcHash: 'h85ac } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30510 : [doRespLdMem] 'h16; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 64 <= 3ffdff00200004000fff00001fffff44000000 + 30510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f88, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a0 } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080011010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a0 } + 30510 : [Ld resp] 'h14; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False } } + 30510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30510 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000f80 +After delta: vaddr = 0x80000f80 + 30510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ac } +calling cycle + 30520 : [doFinishMem] DTlbResp { resp: <'h0000000080000f88,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f88 o: 'h0000000080000f88 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f88, check_high: 'h00000000080000f90, check_inclusive: True } }, specBits: 'h000 } + 30520 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h00, paddr: 'h0000000080000f88, shiftedBE: tagged DataMemAccess , pcHash: 'h85b6 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30520 : [doRespLdMem] 'h14; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0d <= 0000000000000000000000001fffff44000000 + 30520 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080000f60 o: 'h0000000080000f60 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000f80, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ac } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080000f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85ac } + 30520 : [Ld resp] 'h17; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } } + 30520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000008, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b6 } +calling cycle +[RFile] wr_ 0: r 5a <= 00000000200003e4000000001fffff44000000 +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h14, instTag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0d, isFpuReg: False }, paddr: 'h0000000080011010, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30530 : [doFinishMem] DTlbResp { resp: <'h0000000080000f80,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000f80 o: 'h0000000080000f80 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000f80, check_high: 'h00000000080000f88, check_inclusive: True } }, specBits: 'h000 } + 30530 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080000f80, shiftedBE: tagged DataMemAccess , pcHash: 'h85b8 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 30530 : [doRespLdMem] 'h17; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6e <= 0000000020004404000000001fffff44000000 + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b6 } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080000f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b6 } + 30530 : [Ld resp] 'h00; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } } + 30530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000008, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Valid 'h0d, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 33550328 +Before delta: vaddr = 0x80001008 +After delta: vaddr = 0x82000000 + 30530 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + 30530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b8 } calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h15, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30540 : [doRespLdMem] 'h00; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 5b <= 0000000020000095800000001fffff44000000 + 30540 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000008, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'hfff7fc0080001000 o: 'hfff7fc0080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000082000000 o: 'hfff0000082000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000082000000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b8 } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080000f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b8 } + 30540 : [Ld resp] 'h01; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } } + 30540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 30540 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Valid 'h64, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80011010 +After delta: vaddr = 0x80011010 +instret:375 PC:0x1ffff00000000000000000000800005a0 instr:0x00006108 iType:Ld [doCommitNormalInst [0]] 3054 calling cycle -instret:525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3237 + 30550 : [doFinishMem] DTlbResp { resp: <'h0000000082000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000082000000 o: 'hfff0000082000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000082000000, check_high: 'h00000000082000008, check_inclusive: True } }, specBits: 'h000 } + 30550 : [doRespLdMem] 'h01; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 6c <= 00000000200003f0000000001fffff44000000 + 30550 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'hfff7fc0080001000 o: 'hfff7fc0080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080011010, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc +instret:376 PC:0x1ffff00000000000000000000800005a2 instr:0xfd843583 iType:Ld [doCommitNormalInst [0]] 3055 calling cycle + 30560 : [doFinishMem] DTlbResp { resp: <'h0000000080011010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080011010 o: 'h0000000080011010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080011010, check_high: 'h00000000080011018, check_inclusive: True } }, specBits: 'h000 } +instret:377 PC:0x1ffff00000000000000000000800005a6 instr:0x0000e588 iType:St [doCommitNormalInst [0]] 3056 calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h16, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False }, paddr: 'h0000000080000f68, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000082000000, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85a6 } + 30570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a6 } calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h17, instTag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080000f70, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000041000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a6 } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000082000000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85a6 } +[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:378 PC:0x1ffff00000000000000000000800005a8 instr:0xfd843503 iType:Ld [doCommitNormalInst [0]] 3058 calling cycle +instret:379 PC:0x1ffff00000000000000000000800005ac instr:0xfe043583 iType:Ld [doCommitNormalInst [0]] 3059 +instret:380 PC:0x1ffff00000000000000000000800005b0 instr:0x0000e188 iType:St [doCommitNormalInst [1]] 3059 calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False }, paddr: 'h0000000080000f88, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } +[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080011010, isMMIO: False, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h85b0 } + 30600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080011010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b0 } +instret:381 PC:0x1ffff00000000000000000000800005b2 instr:0x0040006f iType:J [doCommitNormalInst [0]] 3060 calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False }, paddr: 'h0000000080000f80, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040008, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080011010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b0 } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080011010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h85b0 } +[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: , shiftedData: TaggedData { tag: False, data: } } + 30610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:382 PC:0x1ffff00000000000000000000800005b6 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 3061 calling cycle +instret:383 PC:0x1ffff00000000000000000000800005b8 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 3062 +instret:384 PC:0x1ffff00000000000000000000800005ba instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 3062 calling cycle +instret:385 PC:0x1ffff00000000000000000000800005bc instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3063 calling cycle -instret:526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3246 calling cycle calling cycle calling cycle @@ -10798,7 +10566,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3255 calling cycle calling cycle calling cycle @@ -10808,7 +10575,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3264 calling cycle calling cycle calling cycle @@ -10818,7 +10584,6 @@ calling cycle calling cycle calling cycle calling cycle -instret:529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3273 calling cycle calling cycle calling cycle @@ -10827,61312 +10592,273 @@ calling cycle calling cycle calling cycle calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle -instret:530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3282 + 31000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h7 } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 31010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb8 +After delta: vaddr = 0x80000fb8 + 31010 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle + 31020 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31020 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fb0 +After delta: vaddr = 0x80000fb0 calling cycle + 31030 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb8 o: 'h0000000080000fb8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb8, check_high: 'h00000000080000fc0, check_inclusive: True } }, specBits: 'h000 } + 31030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080000fb8, shiftedBE: tagged DataMemAccess , pcHash: 'h8256 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31030 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080000f90 o: 'h0000000080000f90 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fb0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8256 } calling cycle +[RFile] wr_ 1: r 7b <= 00000000200003f0000000001fffff44000000 + 31040 : [doFinishMem] DTlbResp { resp: <'h0000000080000fb0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fb0 o: 'h0000000080000fb0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fb0, check_high: 'h00000000080000fb8, check_inclusive: True } }, specBits: 'h000 } + 31040 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080000fb0, shiftedBE: tagged DataMemAccess , pcHash: 'h8258 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8256 } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080000fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8256 } + 31040 : [Ld resp] 'h02; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } } + 31040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle + 31050 : [doRespLdMem] 'h02; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 66 <= 000000002000003b000000001fffff44000000 + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080000fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8258 } + 31050 : [Ld resp] 'h03; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } } + 31050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31050 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000028, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000030 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False }, paddr: 'h0000000080000fb8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31060 : [doRespLdMem] 'h03; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 63 <= 0000000020000400000000001fffff44000000 + 31060 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000028, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe8 +After delta: vaddr = 0x80000fe8 + 31060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000020, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False }, paddr: 'h0000000080000fb0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31070 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000028, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000020, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 +instret:386 PC:0x1ffff0000000000000000000080000256 instr:0x000070a2 iType:Ld [doCommitNormalInst [0]] 3107 calling cycle -calling cycle -instret:531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 3993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4461 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4470 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4479 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4488 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4497 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4506 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4515 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4533 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4542 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4551 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4560 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4569 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4578 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4587 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4596 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4605 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4614 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4623 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4632 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4641 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4650 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4659 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4668 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4677 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4686 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4695 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4704 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4713 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4722 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4731 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4740 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4749 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4758 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4767 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4776 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4785 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4794 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4803 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4812 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4821 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4830 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4839 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4848 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4857 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4866 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4875 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4884 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4893 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4902 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4911 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4920 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4929 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4938 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4947 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4956 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4965 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4974 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4983 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 4992 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5001 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5010 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5019 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5028 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5037 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5046 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5055 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5064 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5073 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5082 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5091 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5109 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5118 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5127 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5136 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5145 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5154 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5163 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5172 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5181 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5190 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5199 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5208 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5217 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5226 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5235 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5244 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5253 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5262 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5271 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5280 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5289 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5298 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5307 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5316 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5325 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5334 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5343 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5352 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5361 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5370 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5379 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5388 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5397 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5415 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5424 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5433 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5442 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5451 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5460 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5469 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5478 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5487 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5496 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5505 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5523 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5532 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5541 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5550 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5559 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5568 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5577 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5586 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5595 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5604 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5613 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5622 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5631 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5640 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5649 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5658 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5667 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5676 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5685 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5694 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5703 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5712 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5721 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5730 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5739 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5748 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5757 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5766 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5775 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5784 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5793 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5802 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5811 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5820 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5829 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5838 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5847 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5856 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5865 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5874 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5883 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5892 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5901 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5910 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5919 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5928 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5937 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5946 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5955 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5964 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5973 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5982 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 5991 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6009 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6018 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6027 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6036 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6045 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6054 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6063 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6072 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6081 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6090 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6099 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6108 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6117 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6126 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6135 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6153 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6162 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6171 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6180 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6189 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6198 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6207 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6216 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6225 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6234 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6243 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6252 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6261 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6270 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6288 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6297 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6306 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6315 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6324 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6333 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6342 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6351 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6360 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6369 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6378 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6387 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6396 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6405 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6414 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6423 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6432 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6441 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6450 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6459 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6468 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6495 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6504 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6513 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6522 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6531 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6540 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6549 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6558 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6567 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6576 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6585 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6594 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6603 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6621 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6630 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6639 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6648 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6657 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6666 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6675 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6684 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6693 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6711 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6720 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6729 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6738 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6747 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6756 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6765 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6774 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6783 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6792 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6801 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6810 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6819 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6828 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6837 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6846 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6855 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6864 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6873 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6882 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6891 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6900 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6909 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6918 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6927 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6936 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6945 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6954 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6963 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6972 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6981 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6990 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 6999 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7008 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7017 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7026 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7035 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7044 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7053 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7062 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7071 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7080 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7089 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7098 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7107 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7116 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7125 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7134 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7143 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7152 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7161 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7170 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7179 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7188 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7197 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7206 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7215 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7224 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7233 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7242 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7251 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7260 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7269 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7287 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7296 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7305 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7314 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7323 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7332 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7341 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7350 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7359 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7368 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7377 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7386 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7404 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7413 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7422 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7431 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7440 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7449 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7458 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7467 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7476 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7485 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7494 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7503 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7512 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7521 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7530 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7539 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7548 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7557 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7566 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7575 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7584 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7593 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7602 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7611 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7620 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7629 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7638 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7647 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7656 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7665 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7674 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7683 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7692 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7701 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7710 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7719 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7728 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7737 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7746 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7755 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7764 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7773 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7782 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7791 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7800 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7809 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7818 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7827 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7836 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7845 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7854 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7863 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7872 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7881 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7890 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7899 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7908 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7917 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7926 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7935 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7944 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7953 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7962 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7971 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7980 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7989 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 7998 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8007 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8016 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8025 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8034 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8043 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8052 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8061 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8070 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8079 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8088 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8097 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8106 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8115 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8124 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8133 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8142 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8151 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8160 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8169 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8178 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8187 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8196 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8205 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8214 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8223 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8232 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8241 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8250 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8259 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8268 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8277 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8286 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8295 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8304 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8313 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8322 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8331 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8340 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8349 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8358 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8367 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8376 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8385 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8394 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8403 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8412 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8421 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8430 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8439 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8448 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8457 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8466 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8475 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8484 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8493 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8502 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8511 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8520 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8529 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8538 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8547 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8556 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8565 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8574 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8583 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8592 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8601 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8610 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8619 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8628 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8637 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8646 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8655 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8664 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8673 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8682 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8691 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8700 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8709 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8718 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8727 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8736 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8745 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8754 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8763 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8772 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8781 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8790 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8799 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8808 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8817 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8826 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8835 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8844 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8862 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8871 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8880 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8889 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8898 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8907 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8916 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8925 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8934 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8943 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8952 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8961 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8970 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8979 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8988 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 8997 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9006 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9015 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9024 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9033 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9042 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9051 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9060 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9069 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9087 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9096 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9105 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9114 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9123 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9132 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9141 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9150 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9159 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9168 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9177 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9186 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9195 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9204 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9213 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9222 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9231 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9240 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9249 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9258 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9267 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9276 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9285 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9294 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9303 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9312 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9321 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9330 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9339 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9348 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9357 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9366 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9375 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9384 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9393 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9402 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9411 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9420 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9429 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9438 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9447 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9456 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9465 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9474 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9483 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9492 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9501 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9510 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9519 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9528 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9537 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9546 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9555 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9564 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9573 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9582 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9591 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9600 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9609 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9618 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9627 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9636 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9645 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9654 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9663 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9672 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9681 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9690 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9699 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9708 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9717 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9726 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9735 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9744 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9762 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9771 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9780 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9789 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9798 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9807 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9816 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9825 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9834 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9843 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9852 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9861 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9870 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9879 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9888 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9897 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9906 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9915 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9924 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9933 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9942 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9951 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9960 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9969 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9978 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9987 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 9996 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10005 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10014 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10023 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10032 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10041 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10050 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10059 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10068 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10077 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10086 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10095 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10104 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10113 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10122 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10131 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10140 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10149 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10158 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10167 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10176 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10185 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10194 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10203 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10212 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10221 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10230 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10239 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10248 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10266 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10275 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10284 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10293 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10302 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10311 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10320 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10329 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10338 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10347 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10356 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10365 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10374 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10383 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10392 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10401 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10410 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10419 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10428 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10437 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10446 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10455 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10464 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10473 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10482 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10491 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10500 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10509 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10518 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10527 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10536 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10545 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10554 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10563 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10572 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10581 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10599 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10608 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10617 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10626 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10635 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10653 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10662 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10671 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10680 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10689 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10698 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10707 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10716 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10725 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10734 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10743 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10752 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10761 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10770 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10779 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10788 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10797 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10806 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10815 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10824 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10842 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10851 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10860 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10869 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10878 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10887 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10896 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10905 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10914 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10923 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10932 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10941 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10950 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10959 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10968 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10977 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10986 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 10995 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11004 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11013 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11022 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11031 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11040 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11049 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11058 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11067 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11076 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11085 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11094 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11103 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11112 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11121 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11130 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11139 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11148 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11157 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11166 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11175 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11184 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11193 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11202 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11211 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11220 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11229 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11238 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11247 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11256 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11265 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11274 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11283 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11292 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11301 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11310 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11319 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11328 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11337 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11346 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11355 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11364 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11373 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11382 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11391 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11400 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11409 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11418 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11427 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11436 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11445 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11454 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11463 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11472 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11481 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11490 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11499 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11508 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11517 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11526 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11535 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11544 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11553 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11562 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11571 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11580 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11589 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11598 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11607 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11616 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11625 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11634 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11643 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11652 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11661 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11670 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11679 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11688 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11697 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11706 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11715 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11724 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11733 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11742 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11751 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11760 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11769 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11778 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11787 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11796 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11805 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11814 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11823 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11832 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11841 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11850 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11859 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11868 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11877 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11886 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11895 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11904 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11922 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11931 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11940 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11949 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11958 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11967 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11976 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11985 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 11994 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12003 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12012 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12021 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12030 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12039 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12048 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12057 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12066 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12075 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12084 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12093 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12102 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12111 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12120 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12129 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12138 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12147 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12156 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12165 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12174 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12183 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12192 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12201 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12210 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12219 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12228 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12237 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12246 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12255 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12264 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12273 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12282 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 12993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13461 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13470 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13479 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13488 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13497 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13506 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13515 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13533 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13542 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13551 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13560 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13569 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13578 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13587 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13596 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13605 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13614 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13623 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13632 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13641 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13650 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13659 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13668 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13677 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13686 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13695 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13704 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13713 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13722 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13731 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13740 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13749 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13758 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13767 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13776 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13785 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13794 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13803 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13812 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13821 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13830 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13839 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13848 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13857 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13866 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13875 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13884 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13893 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13902 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13911 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13920 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13929 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13938 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13947 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13956 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13965 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13974 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13983 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 13992 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14001 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14010 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14019 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14028 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14037 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14046 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14055 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14064 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14073 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14082 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14091 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14109 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14118 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14127 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14136 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14145 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14154 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14163 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14172 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14181 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14190 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14199 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14208 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14217 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14226 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14235 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14244 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14253 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14262 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14271 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14280 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14289 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14298 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14307 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14316 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14325 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14334 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14343 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14352 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14361 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14370 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14379 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14388 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14397 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14415 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14424 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14433 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14442 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14451 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14460 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14469 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14478 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14487 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14496 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14505 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14523 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14532 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14541 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14550 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14559 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14568 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14577 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14586 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14595 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14604 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14613 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14622 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14631 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14640 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14649 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14658 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14667 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14676 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14685 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14694 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14703 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14712 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14721 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14730 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14739 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14748 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14757 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14766 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14775 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14784 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14793 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14802 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14811 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14820 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14829 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14838 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14847 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14856 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14865 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14874 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14883 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14892 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14901 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14910 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14919 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14928 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14937 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14946 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14955 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14964 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14973 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14982 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 14991 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15009 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15018 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15027 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15036 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15045 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15054 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15063 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15072 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15081 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15090 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15099 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15108 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15117 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15126 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15135 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15153 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15162 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15171 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15180 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15189 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15198 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15207 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15216 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15225 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15234 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15243 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15252 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15261 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15270 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15288 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15297 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15306 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15315 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15324 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15333 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15342 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15351 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15360 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15369 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15378 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15387 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15396 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15405 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15414 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15423 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15432 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15441 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15450 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15459 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15468 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15495 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15504 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15513 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15522 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15531 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15540 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15549 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15558 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15567 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15576 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15585 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15594 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15603 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15621 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15630 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15639 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15648 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15657 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15666 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15675 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15684 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15693 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15711 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15720 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15729 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15738 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15747 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15756 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15765 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15774 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15783 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15792 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15801 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15810 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15819 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15828 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15837 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15846 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15855 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15864 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15873 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15882 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15891 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15900 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15909 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15918 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15927 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15936 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15945 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15954 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15963 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15972 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15981 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15990 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 15999 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16008 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16017 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16026 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16035 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16044 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16053 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16062 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16071 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16080 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16089 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16098 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16107 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16116 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16125 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16134 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16143 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16152 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16161 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16170 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16179 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16188 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16197 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16206 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16215 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16224 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16233 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16242 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16251 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16260 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16269 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16287 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16296 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16305 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16314 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16323 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16332 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16341 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16350 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16359 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16368 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16377 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16386 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16404 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16413 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16422 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16431 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16440 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16449 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16458 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16467 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16476 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16485 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16494 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:1999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16503 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16512 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16521 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16530 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16539 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16548 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16557 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16566 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16575 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16584 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16593 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16602 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16611 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16620 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16629 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16638 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16647 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16656 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16665 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16674 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16683 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16692 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16701 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16710 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16719 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16728 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16737 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16746 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16755 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16764 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16773 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16782 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16791 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16800 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16809 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16818 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16827 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16836 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16845 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16854 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16863 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16872 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16881 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16890 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16899 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16908 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16917 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16926 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16935 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16944 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16953 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16962 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16971 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16980 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16989 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 16998 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17007 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17016 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17025 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17034 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17043 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17052 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17061 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17070 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17079 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17088 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17097 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17106 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17115 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17124 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17133 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17142 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17151 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17160 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17169 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17178 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17187 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17196 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17205 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17214 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17223 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17232 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17241 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17250 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17259 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17268 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17277 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17286 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17295 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17304 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17313 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17322 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17331 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17340 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17349 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17358 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17367 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17376 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17385 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17394 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17403 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17412 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17421 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17430 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17439 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17448 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17457 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17466 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17475 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17484 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17493 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17502 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17511 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17520 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17529 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17538 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17547 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17556 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17565 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17574 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17583 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17592 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17601 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17610 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17619 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17628 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17637 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17646 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17655 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17664 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17673 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17682 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17691 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17700 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17709 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17718 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17727 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17736 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17745 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17754 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17763 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17772 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17781 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17790 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17799 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17808 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17817 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17826 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17835 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17844 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17862 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17871 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17880 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17889 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17898 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17907 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17916 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17925 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17934 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17943 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17952 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17961 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17970 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17979 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17988 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 17997 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18006 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18015 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18024 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18033 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18042 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18051 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18060 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18069 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18087 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18096 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18105 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18114 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18123 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18132 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18141 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18150 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18159 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18168 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18177 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18186 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18195 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18204 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18213 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18222 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18231 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18240 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18249 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18258 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18267 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18276 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18285 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18294 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18303 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18312 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18321 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18330 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18339 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18348 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18357 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18366 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18375 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18384 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18393 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18402 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18411 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18420 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18429 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18438 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18447 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18456 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18465 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18474 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18483 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18492 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18501 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18510 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18519 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18528 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18537 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18546 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18555 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18564 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18573 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18582 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18591 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18600 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18609 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18618 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18627 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18636 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18645 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18654 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18663 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18672 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18681 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18690 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18699 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18708 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18717 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18726 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18735 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18744 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18762 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18771 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18780 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18789 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18798 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18807 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18816 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18825 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18834 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18843 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18852 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18861 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18870 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18879 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18888 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18897 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18906 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18915 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18924 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18933 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18942 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18951 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18960 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18969 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18978 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18987 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 18996 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19005 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19014 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19023 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19032 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19041 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19050 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19059 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19068 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19077 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19086 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19095 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19104 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19113 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19122 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19131 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19140 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19149 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19158 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19167 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19176 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19185 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19194 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19203 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19212 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19221 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19230 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19239 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19248 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19266 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19275 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19284 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19293 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19302 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19311 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19320 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19329 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19338 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19347 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19356 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19365 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19374 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19383 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19392 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19401 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19410 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19419 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19428 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19437 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19446 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19455 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19464 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19473 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19482 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19491 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19500 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19509 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19518 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19527 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19536 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19545 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19554 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19563 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19572 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19581 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19599 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19608 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19617 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19626 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19635 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19653 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19662 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19671 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19680 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19689 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19698 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19707 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19716 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19725 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19734 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19743 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19752 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19761 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19770 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19779 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19788 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19797 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19806 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19815 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19824 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19842 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19851 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19860 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19869 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19878 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19887 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19896 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19905 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19914 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19923 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19932 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19941 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19950 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19959 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19968 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19977 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19986 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 19995 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20004 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20013 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20022 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20031 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20040 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20049 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20058 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20067 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20076 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20085 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20094 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20103 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20112 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20121 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20130 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20139 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20148 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20157 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20166 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20175 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20184 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20193 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20202 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20211 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20220 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20229 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20238 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20247 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20256 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20265 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20274 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20283 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20292 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20301 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20310 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20319 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20328 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20337 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20346 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20355 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20364 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20373 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20382 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20391 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20400 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20409 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20418 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20427 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20436 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20445 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20454 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20463 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20472 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20481 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20490 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20499 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20508 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20517 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20526 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20535 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20544 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20553 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20562 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20571 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20580 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20589 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20598 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20607 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20616 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20625 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20634 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20643 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20652 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20661 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20670 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20679 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20688 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20697 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20706 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20715 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20724 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20733 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20742 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20751 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20760 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20769 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20778 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20787 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20796 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20805 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20814 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20823 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20832 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20841 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20850 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20859 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20868 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20877 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20886 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20895 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20904 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20922 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20931 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20940 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20949 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20958 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20967 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20976 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20985 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 20994 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21003 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21012 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21021 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21030 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21039 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21048 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21057 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21066 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21075 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21084 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21093 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21102 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21111 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21120 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21129 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21138 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21147 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21156 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21165 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21174 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21183 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21192 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21201 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21210 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21219 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21228 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21237 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21246 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21255 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21264 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21273 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21282 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 21993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22461 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22470 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22479 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22488 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22497 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22506 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22515 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22533 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22542 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22551 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22560 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22569 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22578 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22587 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22596 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22605 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22614 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22623 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22632 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22641 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22650 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22659 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22668 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22677 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22686 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22695 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22704 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22713 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22722 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22731 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22740 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22749 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22758 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22767 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22776 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22785 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22794 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22803 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22812 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22821 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22830 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22839 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22848 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22857 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22866 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22875 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22884 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22893 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22902 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22911 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22920 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22929 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22938 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22947 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22956 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22965 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22974 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22983 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 22992 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23001 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23010 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23019 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23028 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23037 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23046 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23055 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23064 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23073 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23082 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23091 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23109 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23118 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23127 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23136 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23145 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23154 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23163 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23172 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23181 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23190 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23199 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23208 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23217 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23226 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23235 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23244 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23253 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23262 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23271 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23280 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23289 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23298 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23307 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23316 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23325 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23334 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23343 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23352 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23361 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23370 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23379 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23388 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23397 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23415 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23424 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23433 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23442 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23451 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23460 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23469 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23478 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23487 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23496 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23505 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23523 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23532 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23541 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23550 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23559 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23568 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23577 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23586 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23595 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23604 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23613 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23622 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23631 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23640 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23649 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23658 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23667 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23676 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23685 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23694 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23703 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23712 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23721 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23730 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23739 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23748 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23757 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23766 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23775 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23784 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23793 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23802 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23811 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23820 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23829 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23838 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23847 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23856 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23865 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23874 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23883 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23892 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23901 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23910 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23919 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23928 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23937 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23946 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23955 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23964 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23973 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23982 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 23991 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24009 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24018 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24027 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24036 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24045 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24054 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24063 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24072 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24081 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24090 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24099 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24108 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24117 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24126 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24135 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24153 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24162 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24171 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24180 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24189 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24198 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24207 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24216 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24225 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24234 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24243 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24252 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24261 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24270 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24288 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24297 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24306 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24315 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24324 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24333 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24342 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24351 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24360 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24369 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24378 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24387 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24396 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24405 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24414 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24423 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24432 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24441 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24450 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24459 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24468 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24495 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24504 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24513 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24522 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24531 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24540 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24549 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24558 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24567 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24576 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24585 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24594 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24603 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24621 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24630 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24639 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24648 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24657 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24666 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24675 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24684 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24693 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24711 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24720 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24729 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24738 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24747 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24756 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24765 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24774 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24783 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24792 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24801 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24810 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24819 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24828 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24837 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24846 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24855 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24864 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24873 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24882 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24891 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24900 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24909 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24918 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24927 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24936 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24945 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24954 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24963 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24972 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24981 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24990 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 24999 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25008 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25017 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25026 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25035 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25044 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25053 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25062 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25071 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25080 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25089 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25098 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25107 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25116 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25125 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25134 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25143 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25152 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25161 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25170 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25179 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25188 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25197 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25206 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25215 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25224 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25233 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25242 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25251 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25260 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25269 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25287 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25296 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25305 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25314 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25323 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25332 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25341 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25350 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25359 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25368 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25377 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25386 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25404 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25413 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25422 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25431 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25440 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25449 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25458 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25467 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25476 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25485 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25494 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:2999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25503 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25512 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25521 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25530 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25539 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25548 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25557 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25566 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25575 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25584 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25593 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25602 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25611 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25620 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25629 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25638 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25647 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25656 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25665 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25674 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25683 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25692 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25701 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25710 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25719 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25728 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25737 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25746 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25755 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25764 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25773 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25782 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25791 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25800 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25809 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25818 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25827 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25836 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25845 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25854 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25863 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25872 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25881 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25890 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25899 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25908 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25917 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25926 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25935 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25944 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25953 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25962 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25971 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25980 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25989 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 25998 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26007 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26016 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26025 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26034 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26043 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26052 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26061 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26070 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26079 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26088 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26097 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26106 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26115 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26124 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26133 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26142 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26151 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26160 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26169 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26178 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26187 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26196 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26205 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26214 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26223 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26232 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26241 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26250 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26259 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26268 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26277 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26286 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26295 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26304 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26313 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26322 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26331 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26340 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26349 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26358 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26367 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26376 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26385 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26394 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26403 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26412 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26421 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26430 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26439 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26448 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26457 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26466 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26475 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26484 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26493 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26502 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26511 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26520 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26529 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26538 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26547 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26556 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26565 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26574 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26583 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26592 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26601 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26610 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26619 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26628 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26637 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26646 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26655 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26664 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26673 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26682 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26691 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26700 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26709 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26718 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26727 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26736 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26745 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26754 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26763 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26772 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26781 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26790 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26799 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26808 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26817 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26826 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26835 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26844 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26862 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26871 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26880 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26889 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26898 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26907 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26916 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26925 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26934 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26943 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26952 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26961 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26970 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26979 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26988 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 26997 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27006 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27015 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27024 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27033 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27042 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27051 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27060 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27069 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27087 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27096 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27105 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27114 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27123 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27132 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27141 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27150 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27159 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27168 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27177 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27186 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27195 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27204 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27213 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27222 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27231 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27240 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27249 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27258 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27267 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27276 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27285 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27294 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27303 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27312 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27321 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27330 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27339 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27348 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27357 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27366 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27375 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27384 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27393 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27402 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27411 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27420 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27429 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27438 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27447 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27456 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27465 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27474 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27483 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27492 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27501 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27510 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27519 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27528 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27537 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27546 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27555 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27564 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27573 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27582 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27591 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27600 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27609 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27618 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27627 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27636 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27645 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27654 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27663 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27672 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27681 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27690 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27699 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27708 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27717 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27726 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27735 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27744 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27762 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27771 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27780 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27789 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27798 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27807 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27816 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27825 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27834 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27843 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27852 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27861 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27870 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27879 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27888 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27897 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27906 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27915 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27924 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27933 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27942 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27951 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27960 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27969 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27978 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27987 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 27996 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28005 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28014 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28023 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28032 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28041 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28050 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28059 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28068 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28077 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28086 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28095 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28104 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28113 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28122 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28131 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28140 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28149 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28158 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28167 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28176 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28185 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28194 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28203 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28212 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28221 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28230 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28239 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28248 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28266 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28275 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28284 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28293 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28302 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28311 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28320 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28329 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28338 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28347 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28356 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28365 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28374 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28383 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28392 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28401 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28410 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28419 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28428 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28437 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28446 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28455 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28464 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28473 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28482 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28491 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28500 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28509 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28518 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28527 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28536 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28545 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28554 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28563 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28572 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28581 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28599 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28608 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28617 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28626 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28635 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28653 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28662 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28671 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28680 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28689 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28698 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28707 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28716 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28725 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28734 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28743 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28752 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28761 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28770 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28779 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28788 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28797 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28806 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28815 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28824 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28842 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28851 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28860 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28869 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28878 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28887 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28896 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28905 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28914 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28923 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28932 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28941 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28950 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28959 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28968 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28977 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28986 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 28995 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29004 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29013 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29022 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29031 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29040 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29049 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29058 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29067 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29076 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29085 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29094 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29103 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29112 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29121 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29130 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29139 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29148 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29157 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29166 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29175 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29184 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29193 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29202 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29211 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29220 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29229 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29238 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29247 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29256 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29265 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29274 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29283 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29292 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29301 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29310 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29319 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29328 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29337 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29346 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29355 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29364 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29373 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29382 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29391 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29400 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29409 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29418 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29427 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29436 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29445 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29454 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29463 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29472 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29481 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29490 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29499 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29508 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29517 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29526 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29535 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29544 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29553 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29562 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29571 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29580 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29589 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29598 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29607 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29616 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29625 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29634 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29643 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29652 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29661 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29670 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29679 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29688 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29697 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29706 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29715 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29724 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29733 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29742 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29751 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29760 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29769 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29778 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29787 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29796 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29805 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29814 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29823 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29832 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29841 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29850 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29859 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29868 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29877 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29886 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29895 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29904 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29922 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29931 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29940 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29949 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29958 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29967 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29976 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29985 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 29994 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30003 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30012 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30021 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30030 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30039 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30048 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30057 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30066 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30075 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30084 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30093 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30102 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30111 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30120 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30129 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30138 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30147 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30156 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30165 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30174 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30183 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30192 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30201 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30210 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30219 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30228 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30237 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30246 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30255 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30264 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30273 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30282 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 30993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31461 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31470 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31479 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31488 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31497 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31506 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31515 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31533 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31542 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31551 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31560 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31569 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31578 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31587 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31596 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31605 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31614 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31623 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31632 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31641 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31650 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31659 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31668 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31677 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31686 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31695 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31704 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31713 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31722 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31731 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31740 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31749 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31758 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31767 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31776 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31785 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31794 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31803 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31812 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31821 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31830 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31839 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31848 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31857 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31866 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31875 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31884 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31893 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31902 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31911 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31920 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31929 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31938 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31947 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31956 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31965 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31974 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31983 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 31992 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32001 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32010 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32019 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32028 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32037 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32046 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32055 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32064 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32073 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32082 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32091 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32109 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32118 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32127 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32136 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32145 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32154 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32163 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32172 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32181 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32190 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32199 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32208 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32217 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32226 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32235 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32244 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32253 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32262 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32271 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32280 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32289 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32298 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32307 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32316 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32325 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32334 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32343 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32352 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32361 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32370 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32379 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32388 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32397 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32415 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32424 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32433 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32442 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32451 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32460 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32469 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32478 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32487 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32496 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32505 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32523 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32532 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32541 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32550 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32559 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32568 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32577 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32586 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32595 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32604 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32613 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32622 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32631 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32640 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32649 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32658 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32667 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32676 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32685 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32694 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32703 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32712 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32721 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32730 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32739 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32748 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32757 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32766 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32775 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32784 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32793 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32802 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32811 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32820 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32829 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32838 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32847 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32856 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32865 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32874 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32883 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32892 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32901 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32910 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32919 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32928 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32937 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32946 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32955 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32964 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32973 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32982 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 32991 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33009 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33018 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33027 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33036 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33045 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33054 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33063 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33072 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33081 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33090 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33099 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33108 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33117 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33126 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33135 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33153 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33162 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33171 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33180 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33189 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33198 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33207 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33216 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33225 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33234 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33243 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33252 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33261 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33270 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33288 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33297 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33306 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33315 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33324 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33333 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33342 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33351 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33360 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33369 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33378 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33387 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33396 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33405 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33414 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33423 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33432 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33441 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33450 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33459 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33468 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33495 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33504 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33513 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33522 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33531 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33540 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33549 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33558 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33567 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33576 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33585 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33594 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33603 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33621 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33630 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33639 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33648 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33657 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33666 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33675 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33684 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33693 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33711 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33720 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33729 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33738 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33747 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33756 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33765 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33774 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33783 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33792 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33801 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33810 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33819 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33828 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33837 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33846 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33855 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33864 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33873 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33882 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33891 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33900 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33909 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33918 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33927 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33936 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33945 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33954 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33963 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33972 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33981 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33990 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 33999 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34008 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34017 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34026 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34035 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34044 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34053 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34062 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34071 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34080 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34089 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34098 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34107 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34116 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34125 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34134 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34143 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34152 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34161 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34170 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34179 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34188 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34197 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34206 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34215 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34224 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34233 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34242 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34251 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34260 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34269 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34287 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34296 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34305 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34314 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34323 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34332 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34341 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34350 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34359 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34368 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34377 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34386 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34404 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34413 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34422 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34431 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34440 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34449 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34458 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34467 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34476 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34485 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34494 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:3999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34503 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34512 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34521 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34530 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34539 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34548 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34557 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34566 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34575 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34584 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34593 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34602 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34611 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34620 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34629 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34638 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34647 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34656 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34665 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34674 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34683 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34692 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34701 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34710 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34719 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34728 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34737 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34746 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34755 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34764 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34773 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34782 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34791 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34800 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34809 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34818 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34827 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34836 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34845 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34854 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34863 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34872 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34881 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34890 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34899 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34908 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34917 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34926 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34935 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34944 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34953 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34962 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34971 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34980 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34989 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 34998 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35007 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35016 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35025 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35034 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35043 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35052 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35061 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35070 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35079 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35088 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35097 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35106 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35115 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35124 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35133 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35142 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35151 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35160 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35169 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35178 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35187 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35196 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35205 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35214 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35223 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35232 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35241 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35250 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35259 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35268 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35277 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35286 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35295 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35304 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35313 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35322 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35331 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35340 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35349 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35358 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35367 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35376 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35385 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35394 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35403 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35412 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35421 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35430 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35439 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35448 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35457 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35466 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35475 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35484 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35493 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35502 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35511 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35520 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35529 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35538 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35547 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35556 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35565 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35574 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35583 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35592 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35601 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35610 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35619 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35628 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35637 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35646 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35655 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35664 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35673 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35682 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35691 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35700 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35709 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35718 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35727 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35736 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35745 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35754 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35763 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35772 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35781 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35790 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35799 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35808 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35817 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35826 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35835 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35844 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35862 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35871 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35880 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35889 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35898 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35907 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35916 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35925 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35934 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35943 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35952 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35961 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35970 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35979 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35988 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 35997 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36006 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36015 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36024 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36033 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36042 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36051 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36060 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36069 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36087 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36096 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36105 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36114 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36123 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36132 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36141 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36150 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36159 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36168 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36177 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36186 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36195 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36204 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36213 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36222 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36231 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36240 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36249 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36258 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36267 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36276 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36285 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36294 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36303 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36312 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36321 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36330 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36339 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36348 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36357 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36366 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36375 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36384 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36393 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36402 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36411 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36420 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36429 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36438 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36447 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36456 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36465 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36474 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36483 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36492 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36501 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36510 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36519 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36528 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36537 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36546 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36555 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36564 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36573 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36582 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36591 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36600 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36609 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36618 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36627 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36636 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36645 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36654 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36663 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36672 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36681 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36690 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36699 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36708 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36717 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36726 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36735 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36744 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36762 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36771 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36780 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36789 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36798 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36807 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36816 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36825 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36834 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36843 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36852 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36861 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36870 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36879 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36888 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36897 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36906 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36915 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36924 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36933 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36942 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36951 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36960 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36969 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36978 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36987 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 36996 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37005 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37014 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37023 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37032 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37041 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37050 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37059 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37068 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37077 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37086 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37095 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37104 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37113 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37122 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37131 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37140 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37149 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37158 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37167 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37176 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37185 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37194 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37203 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37212 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37221 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37230 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37239 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37248 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37266 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37275 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37284 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37293 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37302 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37311 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37320 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37329 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37338 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37347 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37356 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37365 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37374 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37383 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37392 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37401 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37410 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37419 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37428 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37437 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37446 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37455 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37464 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37473 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37482 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37491 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37500 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37509 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37518 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37527 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37536 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37545 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37554 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37563 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37572 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37581 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37599 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37608 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37617 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37626 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37635 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37653 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37662 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37671 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37680 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37689 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37698 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37707 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37716 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37725 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37734 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37743 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37752 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37761 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37770 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37779 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37788 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37797 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37806 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37815 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37824 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37842 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37851 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37860 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37869 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37878 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37887 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37896 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37905 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37914 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37923 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37932 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37941 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37950 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37959 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37968 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37977 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37986 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 37995 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38004 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38013 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38022 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38031 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38040 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38049 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38058 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38067 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38076 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38085 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38094 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38103 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38112 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38121 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38130 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38139 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38148 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38157 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38166 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38175 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38184 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38193 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38202 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38211 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38220 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38229 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38238 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38247 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38256 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38265 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38274 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38283 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38292 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38301 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38310 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38319 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38328 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38337 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38346 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38355 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38364 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38373 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38382 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38391 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38400 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38409 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38418 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38427 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38436 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38445 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38454 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38463 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38472 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38481 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38490 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38499 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38508 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38517 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38526 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38535 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38544 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38553 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38562 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38571 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38580 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38589 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38598 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38607 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38616 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38625 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38634 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38643 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38652 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38661 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38670 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38679 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38688 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38697 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38706 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38715 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38724 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38733 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38742 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38751 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38760 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38769 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38778 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38787 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38796 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38805 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38814 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38823 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38832 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38841 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38850 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38859 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38868 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38877 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38886 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38895 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38904 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38922 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38931 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38940 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38949 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38958 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38967 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38976 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38985 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 38994 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39003 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39012 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39021 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39030 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39039 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39048 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39057 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39066 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39075 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39084 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39093 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39102 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39111 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39120 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39129 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39138 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39147 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39156 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39165 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39174 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39183 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39192 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39201 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39210 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39219 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39228 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39237 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39246 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39255 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39264 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39273 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39282 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 39993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40461 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40470 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40479 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40488 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40497 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40506 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40515 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40533 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40542 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40551 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40560 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40569 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40578 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40587 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40596 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40605 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40614 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40623 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40632 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40641 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40650 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40659 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40668 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40677 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40686 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40695 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40704 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40713 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40722 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40731 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40740 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40749 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40758 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40767 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40776 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40785 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40794 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40803 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40812 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40821 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40830 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40839 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40848 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40857 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40866 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40875 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40884 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40893 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40902 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40911 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40920 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40929 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40938 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40947 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40956 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40965 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40974 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40983 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 40992 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41001 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41010 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41019 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41028 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41037 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41046 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41055 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41064 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41073 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41082 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41091 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41109 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41118 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41127 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41136 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41145 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41154 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41163 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41172 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41181 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41190 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41199 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41208 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41217 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41226 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41235 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41244 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41253 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41262 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41271 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41280 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41289 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41298 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41307 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41316 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41325 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41334 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41343 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41352 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41361 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41370 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41379 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41388 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41397 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41415 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41424 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41433 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41442 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41451 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41460 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41469 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41478 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41487 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41496 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41505 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41523 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41532 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41541 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41550 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41559 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41568 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41577 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41586 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41595 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41604 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41613 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41622 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41631 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41640 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41649 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41658 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41667 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41676 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41685 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41694 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41703 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41712 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41721 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41730 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41739 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41748 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41757 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41766 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41775 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41784 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41793 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41802 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41811 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41820 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41829 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41838 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41847 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41856 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41865 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41874 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41883 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41892 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41901 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41910 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41919 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41928 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41937 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41946 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41955 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41964 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41973 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41982 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 41991 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42009 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42018 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42027 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42036 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42045 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42054 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42063 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42072 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42081 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42090 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42099 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42108 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42117 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42126 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42135 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42153 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42162 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42171 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42180 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42189 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42198 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42207 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42216 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42225 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42234 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42243 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42252 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42261 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42270 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42288 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42297 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42306 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42315 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42324 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42333 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42342 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42351 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42360 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42369 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42378 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42387 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42396 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42405 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42414 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42423 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42432 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42441 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42450 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42459 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42468 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42495 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42504 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42513 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42522 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42531 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42540 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42549 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42558 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42567 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42576 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42585 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42594 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42603 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42621 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42630 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42639 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42648 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42657 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42666 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42675 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42684 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42693 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42711 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42720 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42729 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42738 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42747 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42756 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42765 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42774 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42783 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42792 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42801 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42810 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42819 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42828 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42837 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42846 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42855 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42864 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42873 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42882 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42891 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42900 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42909 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42918 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42927 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42936 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42945 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42954 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42963 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42972 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42981 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42990 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 42999 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43008 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43017 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43026 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43035 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43044 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43053 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43062 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43071 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43080 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43089 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43098 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43107 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43116 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43125 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43134 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43143 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43152 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43161 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43170 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43179 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43188 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43197 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43206 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43215 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43224 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43233 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43242 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43251 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43260 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43269 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43287 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43296 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43305 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43314 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43323 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43332 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43341 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43350 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43359 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43368 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43377 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43386 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43404 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43413 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43422 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43431 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43440 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43449 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43458 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43467 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43476 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43485 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43494 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:4999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43503 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43512 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43521 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43530 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43539 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43548 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43557 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43566 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43575 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43584 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43593 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43602 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43611 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43620 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43629 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43638 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43647 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43656 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43665 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43674 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43683 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43692 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43701 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43710 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43719 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43728 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43737 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43746 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43755 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43764 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43773 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43782 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43791 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43800 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43809 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43818 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43827 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43836 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43845 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43854 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43863 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43872 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43881 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43890 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43899 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43908 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43917 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43926 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43935 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43944 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43953 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43962 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43971 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43980 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43989 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 43998 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44007 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44016 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44025 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44034 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44043 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44052 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44061 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44070 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44079 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44088 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44097 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44106 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44115 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44124 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44133 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44142 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44151 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44160 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44169 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44178 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44187 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44196 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44205 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44214 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44223 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44232 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44241 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44250 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44259 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44268 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44277 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44286 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44295 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44304 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44313 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44322 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44331 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44340 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44349 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44358 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44367 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44376 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44385 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44394 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44403 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44412 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44421 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44430 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44439 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44448 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44457 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44466 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44475 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44484 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44493 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44502 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44511 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44520 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44529 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44538 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44547 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44556 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44565 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44574 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44583 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44592 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44601 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44610 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44619 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44628 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44637 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44646 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44655 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44664 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44673 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44682 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44691 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44700 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44709 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44718 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44727 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44736 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44745 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44754 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44763 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44772 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44781 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44790 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44799 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44808 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44817 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44826 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44835 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44844 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44862 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44871 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44880 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44889 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44898 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44907 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44916 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44925 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44934 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44943 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44952 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44961 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44970 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44979 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44988 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 44997 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45006 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45015 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45024 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45033 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45042 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45051 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45060 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45069 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45087 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45096 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45105 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45114 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45123 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45132 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45141 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45150 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45159 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45168 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45177 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45186 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45195 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45204 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45213 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45222 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45231 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45240 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45249 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45258 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45267 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45276 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45285 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45294 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45303 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45312 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45321 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45330 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45339 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45348 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45357 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45366 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45375 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45384 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45393 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45402 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45411 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45420 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45429 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45438 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45447 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45456 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45465 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45474 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45483 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45492 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45501 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45510 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45519 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45528 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45537 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45546 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45555 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45564 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45573 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45582 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45591 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45600 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45609 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45618 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45627 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45636 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45645 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45654 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45663 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45672 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45681 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45690 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45699 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45708 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45717 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45726 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45735 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45744 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45762 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45771 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45780 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45789 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45798 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45807 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45816 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45825 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45834 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45843 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45852 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45861 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45870 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45879 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45888 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45897 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45906 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45915 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45924 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45933 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45942 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45951 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45960 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45969 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45978 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45987 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 45996 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46005 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46014 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46023 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46032 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46041 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46050 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46059 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46068 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46077 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46086 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46095 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46104 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46113 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46122 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46131 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46140 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46149 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46158 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46167 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46176 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46185 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46194 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46203 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46212 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46221 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46230 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46239 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46248 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46266 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46275 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46284 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46293 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46302 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46311 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46320 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46329 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46338 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46347 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46356 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46365 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46374 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46383 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46392 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46401 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46410 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46419 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46428 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46437 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46446 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46455 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46464 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46473 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46482 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46491 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46500 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46509 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46518 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46527 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46536 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46545 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46554 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46563 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46572 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46581 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46599 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46608 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46617 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46626 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46635 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46653 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46662 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46671 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46680 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46689 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46698 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46707 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46716 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46725 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46734 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46743 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46752 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46761 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46770 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46779 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46788 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46797 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46806 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46815 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46824 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46842 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46851 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46860 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46869 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46878 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46887 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46896 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46905 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46914 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46923 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46932 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46941 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46950 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46959 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46968 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46977 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46986 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 46995 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47004 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47013 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47022 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47031 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47040 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47049 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47058 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47067 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47076 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47085 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47094 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47103 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47112 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47121 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47130 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47139 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47148 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47157 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47166 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47175 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47184 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47193 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47202 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47211 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47220 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47229 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47238 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47247 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47256 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47265 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47274 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47283 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47292 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47301 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47310 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47319 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47328 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47337 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47346 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47355 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47364 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47373 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47382 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47391 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47400 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47409 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47418 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47427 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47436 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47445 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47454 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47463 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47472 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47481 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47490 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47499 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47508 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47517 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47526 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47535 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47544 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47553 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47562 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47571 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47580 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47589 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47598 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47607 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47616 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47625 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47634 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47643 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47652 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47661 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47670 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47679 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47688 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47697 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47706 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47715 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47724 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47733 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47742 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47751 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47760 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47769 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47778 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47787 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47796 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47805 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47814 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47823 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47832 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47841 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47850 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47859 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47868 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47877 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47886 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47895 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47904 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47922 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47931 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47940 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47949 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47958 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47967 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47976 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47985 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 47994 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48003 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48012 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48021 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48030 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48039 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48048 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48057 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48066 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48075 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48084 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48093 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48102 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48111 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48120 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48129 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48138 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48147 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48156 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48165 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48174 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48183 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48192 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48201 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48210 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48219 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48228 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48237 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48246 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48255 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48264 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48273 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48282 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 48993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5661 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49461 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5662 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49470 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5663 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49479 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5664 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49488 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5665 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49497 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5666 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49506 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5667 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49515 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5668 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49524 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5669 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49533 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5670 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49542 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5671 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49551 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5672 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49560 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5673 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49569 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5674 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49578 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5675 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49587 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5676 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49596 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5677 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49605 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5678 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49614 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5679 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49623 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5680 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49632 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5681 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49641 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5682 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49650 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5683 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49659 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5684 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49668 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5685 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49677 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5686 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49686 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5687 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49695 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5688 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49704 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5689 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49713 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5690 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49722 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5691 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49731 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5692 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49740 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5693 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49749 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5694 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49758 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5695 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49767 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5696 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49776 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5697 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49785 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5698 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49794 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5699 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49803 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5700 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49812 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5701 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49821 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5702 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49830 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5703 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49839 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5704 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49848 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5705 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49857 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5706 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49866 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5707 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49875 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5708 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49884 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5709 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49893 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5710 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49902 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5711 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49911 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5712 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49920 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5713 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49929 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5714 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49938 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5715 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49947 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5716 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49956 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5717 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49965 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5718 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49974 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5719 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49983 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5720 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 49992 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5721 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50001 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5722 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50010 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5723 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50019 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5724 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50028 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5725 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50037 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5726 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50046 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5727 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50055 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5728 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50064 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5729 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50073 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5730 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50082 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5731 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50091 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5732 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50100 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5733 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50109 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5734 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50118 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5735 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50127 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5736 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50136 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5737 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50145 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5738 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50154 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5739 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50163 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5740 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50172 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5741 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50181 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5742 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50190 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5743 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50199 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5744 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50208 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5745 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50217 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5746 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50226 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5747 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50235 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5748 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50244 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5749 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50253 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5750 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50262 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5751 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50271 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5752 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50280 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5753 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50289 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5754 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50298 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5755 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50307 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5756 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50316 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5757 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50325 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5758 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50334 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5759 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50343 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5760 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50352 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5761 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50361 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5762 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50370 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5763 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50379 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5764 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50388 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5765 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50397 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5766 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50406 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5767 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50415 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5768 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50424 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5769 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50433 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5770 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50442 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5771 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50451 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5772 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50460 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5773 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50469 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5774 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50478 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5775 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50487 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5776 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50496 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5777 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50505 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5778 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50514 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5779 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50523 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5780 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50532 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5781 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50541 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5782 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50550 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5783 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50559 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5784 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50568 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5785 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50577 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5786 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50586 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5787 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50595 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5788 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50604 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5789 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50613 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5790 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50622 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5791 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50631 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5792 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50640 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5793 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50649 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5794 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50658 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5795 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50667 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5796 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50676 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5797 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50685 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5798 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50694 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5799 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50703 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5800 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50712 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5801 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50721 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5802 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50730 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5803 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50739 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5804 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50748 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5805 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50757 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5806 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50766 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5807 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50775 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5808 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50784 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5809 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50793 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5810 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50802 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5811 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50811 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5812 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50820 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5813 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50829 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5814 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50838 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5815 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50847 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5816 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50856 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5817 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50865 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5818 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50874 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5819 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50883 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5820 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50892 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5821 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50901 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5822 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50910 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5823 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50919 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5824 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50928 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5825 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50937 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5826 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50946 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5827 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50955 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5828 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50964 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5829 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50973 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5830 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50982 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5831 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 50991 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5832 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51000 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5833 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51009 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5834 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51018 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5835 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51027 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5836 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51036 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5837 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51045 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5838 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51054 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5839 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51063 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5840 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51072 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5841 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51081 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5842 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51090 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5843 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51099 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5844 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51108 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5845 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51117 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5846 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51126 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5847 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51135 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5848 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51144 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5849 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51153 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5850 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51162 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5851 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51171 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5852 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51180 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5853 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51189 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5854 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51198 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5855 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51207 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5856 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51216 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5857 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51225 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5858 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51234 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5859 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51243 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5860 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51252 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5861 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51261 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5862 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51270 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5863 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51279 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5864 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51288 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5865 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51297 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5866 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51306 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5867 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51315 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5868 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51324 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5869 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51333 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5870 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51342 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5871 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51351 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5872 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51360 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5873 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51369 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5874 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51378 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5875 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51387 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5876 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51396 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5877 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51405 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5878 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51414 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5879 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51423 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5880 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51432 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5881 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51441 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5882 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51450 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5883 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51459 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5884 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51468 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5885 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51477 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5886 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51486 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5887 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51495 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5888 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51504 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5889 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51513 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5890 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51522 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5891 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51531 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5892 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51540 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5893 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51549 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5894 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51558 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5895 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51567 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5896 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51576 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5897 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51585 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5898 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51594 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5899 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51603 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5900 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51612 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5901 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51621 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5902 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51630 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5903 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51639 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5904 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51648 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5905 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51657 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5906 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51666 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5907 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51675 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5908 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51684 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5909 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51693 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5910 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51702 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5911 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51711 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5912 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51720 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5913 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51729 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5914 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51738 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5915 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51747 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5916 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51756 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5917 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51765 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5918 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51774 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5919 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51783 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5920 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51792 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5921 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51801 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5922 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51810 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5923 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51819 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5924 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51828 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5925 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51837 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5926 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51846 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5927 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51855 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5928 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51864 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5929 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51873 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5930 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51882 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5931 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51891 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5932 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51900 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5933 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51909 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5934 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51918 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5935 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51927 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5936 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51936 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5937 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51945 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5938 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51954 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5939 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51963 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5940 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51972 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5941 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51981 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5942 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51990 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5943 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 51999 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5944 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52008 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5945 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52017 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5946 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52026 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5947 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52035 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5948 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52044 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5949 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52053 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5950 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52062 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5951 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52071 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5952 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52080 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5953 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52089 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5954 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52098 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5955 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52107 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5956 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52116 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5957 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52125 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5958 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52134 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5959 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52143 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5960 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52152 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5961 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52161 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5962 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52170 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5963 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52179 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5964 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52188 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5965 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52197 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5966 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52206 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5967 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52215 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5968 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52224 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5969 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52233 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5970 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52242 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5971 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52251 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5972 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52260 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5973 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52269 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5974 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52278 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5975 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52287 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5976 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52296 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5977 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52305 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5978 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52314 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5979 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52323 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5980 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52332 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5981 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52341 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5982 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52350 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5983 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52359 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5984 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52368 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5985 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52377 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5986 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52386 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5987 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52395 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5988 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52404 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5989 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52413 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5990 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52422 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5991 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52431 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5992 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52440 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5993 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52449 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5994 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52458 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5995 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52467 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5996 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52476 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5997 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52485 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5998 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52494 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:5999 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52503 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6000 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52512 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6001 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52521 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6002 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52530 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6003 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52539 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6004 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52548 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6005 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52557 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6006 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52566 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6007 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52575 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6008 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52584 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6009 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52593 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6010 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52602 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6011 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52611 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6012 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52620 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6013 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52629 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6014 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52638 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6015 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52647 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6016 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52656 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6017 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52665 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6018 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52674 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6019 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52683 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6020 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52692 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6021 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52701 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6022 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52710 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6023 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52719 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6024 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52728 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6025 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52737 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6026 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52746 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6027 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52755 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6028 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52764 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6029 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52773 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6030 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52782 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6031 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52791 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6032 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52800 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6033 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52809 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6034 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52818 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6035 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52827 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6036 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52836 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6037 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52845 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6038 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52854 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6039 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52863 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6040 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52872 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6041 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52881 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6042 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52890 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6043 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52899 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6044 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52908 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6045 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52917 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6046 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52926 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6047 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52935 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6048 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52944 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6049 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52953 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6050 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52962 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6051 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52971 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6052 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52980 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6053 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52989 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6054 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 52998 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6055 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53007 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6056 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53016 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6057 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53025 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6058 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53034 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6059 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53043 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6060 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53052 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6061 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53061 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6062 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53070 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6063 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53079 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6064 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53088 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6065 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53097 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6066 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53106 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6067 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53115 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6068 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53124 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6069 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53133 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6070 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53142 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6071 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53151 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6072 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53160 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6073 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53169 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6074 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53178 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6075 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53187 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6076 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53196 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6077 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53205 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6078 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53214 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6079 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53223 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6080 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53232 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6081 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53241 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6082 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53250 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6083 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53259 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6084 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53268 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6085 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53277 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6086 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53286 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6087 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53295 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6088 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53304 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6089 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53313 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6090 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53322 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6091 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53331 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6092 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53340 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6093 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53349 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6094 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53358 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6095 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53367 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6096 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53376 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6097 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53385 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6098 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53394 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6099 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53403 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6100 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53412 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6101 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53421 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6102 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53430 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6103 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53439 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6104 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53448 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6105 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53457 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6106 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53466 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6107 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53475 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6108 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53484 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6109 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53493 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6110 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53502 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6111 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53511 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6112 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53520 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6113 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53529 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6114 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53538 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6115 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53547 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6116 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53556 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6117 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53565 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6118 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53574 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6119 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53583 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6120 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53592 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6121 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53601 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6122 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53610 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6123 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53619 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6124 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53628 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6125 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53637 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6126 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53646 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6127 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53655 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6128 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53664 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6129 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53673 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6130 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53682 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6131 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53691 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6132 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53700 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6133 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53709 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6134 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53718 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6135 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53727 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6136 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53736 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6137 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53745 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6138 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53754 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6139 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53763 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6140 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53772 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6141 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53781 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6142 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53790 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6143 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53799 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6144 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53808 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6145 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53817 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6146 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53826 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6147 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53835 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6148 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53844 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6149 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53853 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6150 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53862 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6151 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53871 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6152 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53880 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6153 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53889 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6154 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53898 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6155 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53907 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6156 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53916 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6157 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53925 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6158 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53934 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6159 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53943 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6160 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53952 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6161 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53961 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6162 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53970 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6163 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53979 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6164 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53988 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6165 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 53997 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6166 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54006 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6167 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54015 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6168 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54024 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6169 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54033 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6170 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54042 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6171 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54051 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6172 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54060 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6173 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54069 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6174 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54078 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6175 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54087 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6176 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54096 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6177 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54105 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6178 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54114 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6179 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54123 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6180 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54132 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6181 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54141 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6182 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54150 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6183 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54159 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6184 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54168 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6185 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54177 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6186 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54186 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6187 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54195 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6188 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54204 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6189 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54213 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6190 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54222 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6191 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54231 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6192 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54240 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6193 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54249 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6194 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54258 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6195 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54267 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6196 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54276 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6197 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54285 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6198 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54294 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6199 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54303 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6200 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54312 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6201 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54321 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6202 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54330 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6203 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54339 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6204 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54348 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6205 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54357 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6206 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54366 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6207 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54375 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6208 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54384 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6209 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54393 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6210 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54402 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6211 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54411 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6212 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54420 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6213 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54429 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6214 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54438 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6215 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54447 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6216 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54456 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6217 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54465 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6218 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54474 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6219 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54483 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6220 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54492 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6221 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54501 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6222 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54510 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6223 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54519 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6224 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54528 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6225 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54537 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6226 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54546 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6227 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54555 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6228 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54564 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6229 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54573 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6230 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54582 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6231 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54591 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6232 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54600 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6233 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54609 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6234 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54618 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6235 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54627 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6236 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54636 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6237 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54645 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6238 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54654 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6239 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54663 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6240 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54672 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6241 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54681 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6242 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54690 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6243 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54699 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6244 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54708 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6245 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54717 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6246 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54726 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6247 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54735 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6248 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54744 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6249 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54753 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6250 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54762 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6251 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54771 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6252 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54780 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6253 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54789 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6254 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54798 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6255 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54807 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6256 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54816 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6257 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54825 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6258 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54834 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6259 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54843 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6260 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54852 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6261 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54861 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6262 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54870 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6263 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54879 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6264 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54888 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6265 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54897 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6266 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54906 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6267 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54915 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6268 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54924 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6269 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54933 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6270 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54942 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6271 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54951 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6272 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54960 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6273 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54969 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6274 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54978 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6275 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54987 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6276 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 54996 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6277 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55005 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6278 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55014 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6279 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55023 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6280 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55032 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6281 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55041 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6282 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55050 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6283 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55059 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6284 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55068 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6285 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55077 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6286 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55086 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6287 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55095 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6288 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55104 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6289 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55113 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6290 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55122 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6291 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55131 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6292 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55140 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6293 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55149 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6294 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55158 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6295 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55167 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6296 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55176 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6297 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55185 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6298 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55194 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6299 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55203 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6300 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55212 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6301 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55221 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6302 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55230 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6303 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55239 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6304 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55248 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6305 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55257 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6306 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55266 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6307 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55275 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6308 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55284 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6309 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55293 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6310 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55302 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6311 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55311 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6312 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55320 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6313 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55329 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6314 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55338 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6315 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55347 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6316 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55356 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6317 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55365 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6318 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55374 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6319 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55383 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6320 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55392 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6321 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55401 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6322 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55410 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6323 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55419 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6324 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55428 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6325 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55437 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6326 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55446 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6327 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55455 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6328 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55464 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6329 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55473 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6330 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55482 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6331 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55491 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6332 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55500 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6333 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55509 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6334 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55518 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6335 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55527 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6336 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55536 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6337 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55545 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6338 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55554 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6339 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55563 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6340 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55572 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6341 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55581 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6342 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55590 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6343 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55599 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6344 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55608 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6345 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55617 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6346 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55626 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6347 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55635 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6348 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55644 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6349 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55653 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6350 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55662 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6351 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55671 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6352 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55680 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6353 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55689 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6354 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55698 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6355 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55707 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6356 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55716 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6357 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55725 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6358 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55734 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6359 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55743 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6360 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55752 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6361 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55761 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6362 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55770 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6363 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55779 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6364 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55788 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6365 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55797 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6366 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55806 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6367 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55815 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6368 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55824 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6369 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55833 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6370 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55842 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6371 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55851 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6372 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55860 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6373 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55869 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6374 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55878 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6375 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55887 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6376 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55896 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6377 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55905 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6378 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55914 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6379 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55923 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6380 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55932 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6381 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55941 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6382 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55950 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6383 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55959 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6384 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55968 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6385 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55977 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6386 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55986 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6387 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 55995 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6388 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56004 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6389 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56013 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6390 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56022 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6391 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56031 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6392 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56040 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6393 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56049 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6394 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56058 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6395 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56067 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6396 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56076 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6397 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56085 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6398 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56094 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6399 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56103 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6400 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56112 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6401 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56121 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6402 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56130 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6403 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56139 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6404 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56148 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6405 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56157 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6406 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56166 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6407 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56175 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6408 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56184 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6409 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56193 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6410 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56202 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6411 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56211 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6412 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56220 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6413 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56229 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6414 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56238 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6415 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56247 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6416 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56256 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6417 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56265 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6418 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56274 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6419 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56283 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6420 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56292 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6421 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56301 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6422 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56310 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6423 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56319 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6424 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56328 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6425 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56337 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6426 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56346 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6427 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56355 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6428 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56364 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6429 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56373 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6430 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56382 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6431 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56391 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6432 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56400 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6433 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56409 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6434 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56418 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6435 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56427 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6436 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56436 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6437 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56445 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6438 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56454 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6439 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56463 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6440 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56472 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6441 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56481 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6442 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56490 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6443 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56499 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6444 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56508 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6445 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56517 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6446 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56526 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6447 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56535 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6448 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56544 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6449 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56553 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6450 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56562 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6451 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56571 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6452 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56580 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6453 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56589 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6454 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56598 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6455 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56607 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6456 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56616 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6457 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56625 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6458 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56634 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6459 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56643 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6460 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56652 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6461 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56661 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6462 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56670 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6463 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56679 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6464 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56688 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6465 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56697 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6466 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56706 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6467 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56715 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6468 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56724 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6469 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56733 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6470 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56742 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6471 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56751 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6472 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56760 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6473 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56769 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6474 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56778 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6475 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56787 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6476 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56796 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6477 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56805 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6478 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56814 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6479 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56823 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6480 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56832 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6481 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56841 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6482 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56850 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6483 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56859 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6484 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56868 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6485 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56877 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6486 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56886 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6487 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56895 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6488 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56904 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6489 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56913 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6490 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56922 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6491 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56931 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6492 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56940 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6493 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56949 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6494 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56958 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6495 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56967 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6496 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56976 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6497 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56985 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6498 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 56994 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6499 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57003 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6500 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57012 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6501 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57021 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6502 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57030 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6503 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57039 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6504 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57048 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6505 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57057 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6506 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57066 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6507 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57075 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6508 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57084 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6509 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57093 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6510 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57102 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6511 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57111 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6512 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57120 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6513 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57129 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6514 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57138 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6515 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57147 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6516 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57156 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6517 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57165 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6518 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57174 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6519 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57183 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6520 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57192 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6521 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57201 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6522 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57210 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6523 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57219 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6524 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57228 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6525 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57237 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6526 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57246 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6527 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57255 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6528 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57264 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6529 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57273 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6530 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57282 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6531 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57291 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6532 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57300 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6533 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57309 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6534 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57318 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6535 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57327 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6536 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57336 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6537 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57345 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6538 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57354 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6539 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57363 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6540 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57372 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6541 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57381 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6542 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57390 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6543 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57399 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6544 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57408 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6545 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57417 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6546 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57426 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6547 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57435 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6548 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57444 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6549 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57453 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6550 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57462 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6551 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57471 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6552 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57480 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6553 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57489 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6554 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57498 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6555 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57507 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6556 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57516 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6557 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57525 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6558 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57534 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6559 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57543 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6560 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57552 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6561 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57561 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6562 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57570 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6563 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57579 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6564 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57588 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6565 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57597 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6566 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57606 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6567 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57615 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6568 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57624 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6569 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57633 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6570 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57642 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6571 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57651 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6572 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57660 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6573 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57669 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6574 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57678 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6575 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57687 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6576 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57696 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6577 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57705 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6578 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57714 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6579 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57723 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6580 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57732 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6581 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57741 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6582 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57750 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6583 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57759 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6584 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57768 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6585 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57777 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6586 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57786 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6587 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57795 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6588 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57804 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6589 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57813 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6590 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57822 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6591 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57831 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6592 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57840 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6593 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57849 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6594 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57858 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6595 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57867 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6596 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57876 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6597 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57885 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6598 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57894 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6599 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57903 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6600 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57912 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6601 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57921 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6602 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57930 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6603 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57939 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6604 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57948 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6605 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57957 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6606 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57966 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6607 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57975 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6608 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57984 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6609 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 57993 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6610 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58002 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6611 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58011 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6612 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58020 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6613 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58029 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6614 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58038 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6615 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58047 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6616 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58056 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6617 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58065 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6618 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58074 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6619 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58083 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6620 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58092 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6621 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58101 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6622 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58110 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6623 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58119 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6624 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58128 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6625 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58137 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6626 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58146 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6627 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58155 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6628 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58164 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6629 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58173 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6630 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58182 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6631 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58191 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6632 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58200 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6633 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58209 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6634 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58218 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6635 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58227 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6636 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58236 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6637 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58245 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6638 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58254 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6639 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58263 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6640 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58272 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6641 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58281 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6642 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58290 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6643 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58299 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6644 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58308 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6645 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58317 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6646 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58326 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6647 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58335 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6648 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58344 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6649 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58353 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6650 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58362 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6651 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58371 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6652 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58380 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6653 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58389 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6654 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58398 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6655 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58407 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6656 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58416 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6657 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58425 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6658 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58434 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6659 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58443 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -instret:6660 PC:0x1ffff0000000000000000000000000000 instr:0x00000000 iType:Unsupported [doCommitTrap] 58452 -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle -calling cycle +[ALU redirect - 1] 'h1ffff00000000000000000000800000ec; 'h0; InstTag { way: 'h1, ptr: 'h12, t: 'h25 } + 31080 : [doFinishMem] DTlbResp { resp: <'h0000000080000fe8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000fe8 o: 'h0000000080000fe8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000fe8, check_high: 'h00000000080000ff0, check_inclusive: True } }, specBits: 'h001 } + 31080 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000fe8, shiftedBE: tagged DataMemAccess , pcHash: 'h8256 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000020, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8256 } +instret:387 PC:0x1ffff0000000000000000000080000258 instr:0x00007402 iType:Ld [doCommitNormalInst [0]] 3108 +instret:388 PC:0x1ffff000000000000000000008000025a instr:0x00006145 iType:Alu [doCommitNormalInst [1]] 3108 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h12, t: 'h25 } ; 'h0 ; 'h1 ; ; ; > ; > ; 'h0 ; ; +calling cycle + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8256 } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080000fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8256 } + 31100 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } } + 31100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:389 PC:0x1ffff000000000000000000008000025c instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3110 +calling cycle + 31110 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: } } +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h02, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h6 } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + 31150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 31150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 +calling cycle +[RFile] wr_ 1: r 02 <= 0000000000000000000000001fffff44000000 + 31170 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 31170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080000ff8, shiftedBE: tagged DataMemAccess , pcHash: 'h80ee } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080000fc0 o: 'h0000000080000fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } +calling cycle +[RFile] wr_ 1: r 7c <= 0000000020000400000000001fffff44000000 + 31180 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } + 31180 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080000ff0, shiftedBE: tagged DataMemAccess , pcHash: 'h80f0 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache + 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080000ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ee } + 31180 : [Ld resp] 'h04; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } } + 31180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f0 } +instret:390 PC:0x1ffff00000000000000000000800000ec instr:0x00004501 iType:Alu [doCommitNormalInst [0]] 3118 +calling cycle + 31190 : [doRespLdMem] 'h04; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 7e <= 0000000020000006000000001fffff44000000 + 31190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f0 } + 31190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080000ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80f0 } + 31190 : [Ld resp] 'h05; TaggedData { tag: False, data: }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False } } + 31190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False }, paddr: 'h0000000080000ff8, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31200 : [doRespLdMem] 'h05; TaggedData { tag: False, data: }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: } } +[RFile] wr_ 3: r 0c <= 0000000000000000000000001fffff44000000 + 31200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h01, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess , unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h0c, isFpuReg: False }, paddr: 'h0000000080000ff0, isMMIO: False, shiftedBE: tagged DataMemAccess , fault: tagged Invalid , allowCap: False, killed: tagged Invalid } + 31210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001038 +After delta: vaddr = 0x80001038 + 31210 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:391 PC:0x1ffff00000000000000000000800000ee instr:0x000070e2 iType:Ld [doCommitNormalInst [0]] 3121 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h4 } }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[ALU redirect - 0] 'h1ffff0000000000000000000080000018; 'h0; InstTag { way: 'h0, ptr: 'h15, t: 'h2a } + 31220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001038 o: 'h0000000080001038 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h001 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001038, write: False, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31220 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80001030 +After delta: vaddr = 0x80001030 +instret:392 PC:0x1ffff00000000000000000000800000f0 instr:0x00007442 iType:Ld [doCommitNormalInst [0]] 3122 +instret:393 PC:0x1ffff00000000000000000000800000f2 instr:0x00006121 iType:Alu [doCommitNormalInst [1]] 3122 +calling cycle +[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h15, t: 'h2a } ; 'h0 ; 'h0 ; ; ; > ; > ; 'h1 ; ; +calling cycle +instret:394 PC:0x1ffff00000000000000000000800000f4 instr:0x00008082 iType:Jr [doCommitNormalInst [0]] 3124 +calling cycle +calling cycle +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h44, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h02, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h78, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h7c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000018, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle + 31300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 44 <= 0000000000000000000000001fffff44000000 +[RFile] wr_ 1: r 78 <= 0000000000000000000000001fffff44000000 + 31310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h44, src2: tagged Valid 'h0b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x00000000 +After delta: vaddr = 0x00000000 + 31310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000018, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 0b <= 0000000000000000400000001fffff44000000 + 31320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h7e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff8 +After delta: vaddr = 0x80000ff8 + 31320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000010, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +instret:395 PC:0x1ffff0000000000000000000080000018 instr:0x0000832a iType:Alu [doCommitNormalInst [0]] 3132 +instret:396 PC:0x1ffff000000000000000000008000001a instr:0x00004281 iType:Alu [doCommitNormalInst [1]] 3132 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 71 <= 00000000200003f8000000001fffff44000000 + 31330 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 } + 31330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000018, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000080000018 o: 'h0000000080000018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff8, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + 31330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000010, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h0c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000ff0 +After delta: vaddr = 0x80000ff0 +instret:397 PC:0x1ffff000000000000000000008000001c instr:0x00004305 iType:Alu [doCommitNormalInst [0]] 3133 + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0b, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000009 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h08, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 6a <= 0000000020000400000000001fffff44000000 + 31340 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff8 o: 'h0000000080000ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff8, check_high: 'h00000000080001000, check_inclusive: True } }, specBits: 'h000 } + 31340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000010, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000ff0, write: True, capStore: False, potentialCapLoad: False } +L1 TLB inc + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 5c <= 40000000000000000000ffff1fffff44000000 +[RFile] wr_ 1: r 46 <= 0000000000020000000000001fffff44000000 + 31350 : [doFinishMem] DTlbResp { resp: <'h0000000080000ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess , vaddr: v: True a: 'h0000000080000ff0 o: 'h0000000080000ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080000ff0, check_high: 'h00000000080000ff8, check_inclusive: True } }, specBits: 'h000 } +[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: , stData: TaggedData { tag: False, data: }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h801e }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: , data: TaggedData { tag: False, data: }, loadTags: False } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 5e <= 0000000000020000400000001fffff44000000 + 31360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffe0, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h7a, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } } +calling cycle +[RFile] wr_ 0: r 76 <= 0000000020000400000000001fffff44000000 + 31370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 + 31370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffe0, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +calling cycle +[RFile] wr_ 1: r 08 <= 0000000020000402400000001fffff44000000 + 31380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffe0, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080000fe0 o: 'h0000000080000fe0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess , shiftBEData: }, spec_bits: 'h000 } +DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080000fe0, write: False, capStore: False, potentialCapLoad: True } +L1 TLB inc + 31380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffe0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 } +Decoded delta from register = 0 +Before delta: vaddr = 0x80000fe0 +After delta: vaddr = 0x80000fe0 + 31380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h5 } }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } + [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000010, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } } +3139: mmioPlatform.rl_tohost: 0x1 (= 1) +PASS