diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 071c975..a282242 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -205,7 +205,7 @@ interface Core; (* always_enabled *) method Tuple2#(CapMem, Bit#(32)) debugLastInst; (* always_enabled *) - method Tuple2#(CapMem, Bit#(32)) debugNextInst; + method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob; `endif endinterface @@ -1455,7 +1455,7 @@ module mkCore#(CoreId coreId)(Core); `ifdef DEBUG_WEDGE method Tuple2#(CapMem, Bit#(32)) debugLastInst = commitStage.debugLastInst; - method Tuple2#(CapMem, Bit#(32)) debugNextInst = rob.debugNextInst; + method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob = rob.debugRob; `endif endmodule diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index 740a52c..c905e20 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -335,7 +335,7 @@ module mkProc (Proc_IFC); `ifdef DEBUG_WEDGE method Tuple2#(CapMem, Bit#(32)) hart0_last_inst = core[0].debugLastInst; - method Tuple2#(CapMem, Bit#(32)) hart0_next_inst = core[0].debugNextInst; + method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) hart0_debug_rob = core[0].debugRob; `endif endmodule: mkProc diff --git a/src_Core/CPU/Proc_IFC.bsv b/src_Core/CPU/Proc_IFC.bsv index dca743b..161a2a9 100644 --- a/src_Core/CPU/Proc_IFC.bsv +++ b/src_Core/CPU/Proc_IFC.bsv @@ -137,7 +137,7 @@ interface Proc_IFC; (* always_enabled *) method Tuple2#(CapMem, Bit#(32)) hart0_last_inst; (* always_enabled *) - method Tuple2#(CapMem, Bit#(32)) hart0_next_inst; + method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) hart0_debug_rob; `endif endinterface diff --git a/src_Core/Core/CoreW.bsv b/src_Core/Core/CoreW.bsv index d573715..48d07a6 100644 --- a/src_Core/Core/CoreW.bsv +++ b/src_Core/Core/CoreW.bsv @@ -234,7 +234,7 @@ module mkCoreW #(Reset dm_power_on_reset) `ifdef DEBUG_WEDGE mkConnection (proc.hart0_last_inst, debug_module.hart0_last_inst); - mkConnection (proc.hart0_next_inst, debug_module.hart0_next_inst); + mkConnection (proc.hart0_debug_rob, debug_module.hart0_debug_rob); `endif `endif diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index 1d3043a..6cbc582 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -138,7 +138,7 @@ interface Debug_Module_IFC; method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst); (* always_enabled *) - method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst); + method Action hart0_debug_rob (Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) state); `endif // ---------------- @@ -172,8 +172,20 @@ module mkDebug_Module (Debug_Module_IFC); `ifdef DEBUG_WEDGE Reg #(CapMem) rg_last_pcc <- mkConfigReg (unpack (0)); Reg #(Bit #(32)) rg_last_inst <- mkConfigReg (0); - Reg #(CapMem) rg_next_pcc <- mkConfigReg (unpack (0)); - Reg #(Bit #(32)) rg_next_inst <- mkConfigReg (0); + + Reg #(Bit #(32)) rg_rob_ps_and_ways <- mkConfigReg (0); + Reg #(Bit #(32)) rg_rob_valid0 <- mkConfigReg (0); + Reg #(Bit #(32)) rg_rob_valid1 <- mkConfigReg (0); + + Reg #(CapMem) rg_rob_first0_pcc <- mkConfigReg (unpack (0)); + Reg #(Bit #(32)) rg_rob_first0_inst <- mkConfigReg (0); + Reg #(CapMem) rg_rob_first1_pcc <- mkConfigReg (unpack (0)); + Reg #(Bit #(32)) rg_rob_first1_inst <- mkConfigReg (0); + + Reg #(CapMem) rg_rob_last0_pcc <- mkConfigReg (unpack (0)); + Reg #(Bit #(32)) rg_rob_last0_inst <- mkConfigReg (0); + Reg #(CapMem) rg_rob_last1_pcc <- mkConfigReg (unpack (0)); + Reg #(Bit #(32)) rg_rob_last1_inst <- mkConfigReg (0); `endif // ================================================================ @@ -257,23 +269,63 @@ module mkDebug_Module (Debug_Module_IFC); else if (dm_addr == dm_addr_custom1) - dm_word = getAddr (rg_last_pcc) [63:32]; + dm_word = rg_rob_ps_and_ways; else if (dm_addr == dm_addr_custom2) - dm_word = rg_last_inst; + dm_word = rg_rob_valid0; else if (dm_addr == dm_addr_custom3) - dm_word = getAddr (rg_next_pcc) [31:0]; + dm_word = rg_rob_valid1; else if (dm_addr == dm_addr_custom4) - dm_word = getAddr (rg_next_pcc) [63:32]; + dm_word = getAddr (rg_rob_first0_pcc) [31:0]; else if (dm_addr == dm_addr_custom5) - dm_word = rg_next_inst; + dm_word = getAddr (rg_rob_first0_pcc) [63:32]; + + else if (dm_addr == dm_addr_custom6) + + dm_word = rg_rob_first0_inst; + + else if (dm_addr == dm_addr_custom7) + + dm_word = getAddr (rg_rob_first1_pcc) [31:0]; + + else if (dm_addr == dm_addr_custom8) + + dm_word = getAddr (rg_rob_first1_pcc) [63:32]; + + else if (dm_addr == dm_addr_custom9) + + dm_word = rg_rob_first1_inst; + + else if (dm_addr == dm_addr_custom10) + + dm_word = getAddr (rg_rob_last0_pcc) [31:0]; + + else if (dm_addr == dm_addr_custom11) + + dm_word = getAddr (rg_rob_last0_pcc) [63:32]; + + else if (dm_addr == dm_addr_custom12) + + dm_word = rg_rob_last0_inst; + + else if (dm_addr == dm_addr_custom13) + + dm_word = getAddr (rg_rob_last1_pcc) [31:0]; + + else if (dm_addr == dm_addr_custom14) + + dm_word = getAddr (rg_rob_last1_pcc) [63:32]; + + else if (dm_addr == dm_addr_custom15) + + dm_word = rg_rob_last1_inst; `endif else begin @@ -370,9 +422,33 @@ module mkDebug_Module (Debug_Module_IFC); rg_last_inst <= tpl_2 (pcc_inst); endmethod - method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst); - rg_next_pcc <= tpl_1 (pcc_inst); - rg_next_inst <= tpl_2 (pcc_inst); + // XXX: Yes the extra void at the end of the tuple is necessary. Without it, + // bsc seems to inline the last tuple and destroy the programmer-visible + // structure, such that the assignments to rg_rob_lastX_foo need to be + // tpl_[3456] (state), *not* tpl_[1234] (tpl_3 (state)), with the latter + // giving: + // + // The provisos for this expression could not be resolved because there are no + // instances of the form: + // Has_tpl_1#(Bit#(32), Bit#(129)) + // + // for the assignment to rg_rob_last0_pcc, and similarly for the others if + // you comment that one out. Just because they're isomorphic doesn't mean + // they're interchangeable :(. + method Action hart0_debug_rob (Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) state); + rg_rob_ps_and_ways <= tpl_1 (tpl_1 (state)); + rg_rob_valid0 <= tpl_2 (tpl_1 (state)); + rg_rob_valid1 <= tpl_3 (tpl_1 (state)); + + rg_rob_first0_pcc <= tpl_1 (tpl_2 (state)); + rg_rob_first0_inst <= tpl_2 (tpl_2 (state)); + rg_rob_first1_pcc <= tpl_3 (tpl_2 (state)); + rg_rob_first1_inst <= tpl_4 (tpl_2 (state)); + + rg_rob_last0_pcc <= tpl_1 (tpl_3 (state)); + rg_rob_last0_inst <= tpl_2 (tpl_3 (state)); + rg_rob_last1_pcc <= tpl_3 (tpl_3 (state)); + rg_rob_last1_inst <= tpl_4 (tpl_3 (state)); endmethod `endif diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index dd56b39..44d2cd7 100755 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -681,7 +681,7 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum `ifdef DEBUG_WEDGE (* always_enabled *) - method Tuple2#(CapMem, Bit#(32)) debugNextInst; + method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob; `endif endinterface @@ -1337,8 +1337,32 @@ module mkSupReorderBuffer#( endinterface `ifdef DEBUG_WEDGE - method Tuple2#(CapMem, Bit#(32)) debugNextInst; - return tuple2(fifo_first[0].pc, fifo_first[0].orig_inst); + // See Debug_Module.bsv for why this "pointless" void tuple component is + // added at the end (bsc bug). + method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob; + Bit#(8) enqP0 = zeroExtend(enqP[0]); + Bit#(7) enqP1 = zeroExtend(enqP[1]); + Bit#(16) enqPsAndWay = {firstEnqWay, enqP1, enqP0}; + + Bit#(8) deqP0 = zeroExtend(deqP[0]); + Bit#(7) deqP1 = zeroExtend(deqP[1]); + Bit#(16) deqPsAndWay = {firstDeqWay, deqP1, deqP0}; + + Bit#(32) bothPsAndWays = {deqPsAndWay, enqPsAndWay}; + + let first0 = row[0][deqP0].read_deq; + let first1 = row[1][deqP1].read_deq; + + let last0 = row[0][enqP0 - 1].read_deq; + let last1 = row[1][enqP1 - 1].read_deq; + + function a readReg(Reg#(a) r) provisos(Bits#(a, aSz)) = r; + function Vector#(n, a) readVector(Vector#(n, Reg#(a)) vr) provisos(Bits#(a, aSz)) = map(readReg, vr); + + Bit#(32) valid0 = pack(readVector(getVEhrPort(valid[0], 0))); + Bit#(32) valid1 = pack(readVector(getVEhrPort(valid[1], 0))); + + return tuple4(tuple3(bothPsAndWays, valid0, valid1), tuple4(first0.pc, first0.orig_inst, first1.pc, first1.orig_inst), tuple4(last0.pc, last0.orig_inst, last1.pc, last1.orig_inst), ?); endmethod `endif endmodule