From 10c983d101a0602c706ea00a9424879ee76beb9c Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Wed, 8 Apr 2020 04:22:49 +0100 Subject: [PATCH] FetchStage.bsv: Drop unused pc from Fetch3ToDecode Each instruction carries its own PC by this point, so it just duplicates the PC of the first item in the vector. Moreover, when including a pending straddle at the head, the PC value was not set to the previous half's, ie PC-2. We keep pred_next_pc as that's used to determine where the bundle is predicted to go next, and the duplication avoids having to dynamically index the vector based on the number of instructions fed to decode. --- src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 3 --- 1 file changed, 3 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index bd8a66b..a10af69 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -125,7 +125,6 @@ typedef struct { } Fetch2ToFetch3 deriving(Bits, Eq, FShow); typedef struct { - Addr pc; Addr pred_next_pc; Bool mispred_first_half; Maybe#(Exception) cause; @@ -692,7 +691,6 @@ module mkFetchStage(FetchStage); if (pending_n_items == 0) begin out = Fetch3ToDecode { - pc: fetch3In.pc, pred_next_pc: pred_next_pc, mispred_first_half: mispred_first_half, cause: fetch3In.cause, @@ -742,7 +740,6 @@ module mkFetchStage(FetchStage); next_pending_n_items = truncate(n_items - fromInteger(valueOf(SupSize))); rg_pending_decode <= drop(v_items); rg_pending_f32d <= Fetch3ToDecode { - pc: v_items[valueOf(SupSize)].pc, pred_next_pc: out.pred_next_pc, mispred_first_half: False, cause: tagged Invalid,