Added support for 'debug_external_interrupt_req'

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New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.

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This commit is contained in:

rsnikhil

2019-04-01 12:26:54 -04:00

parent 85b745be9f

commit 113f888d37

346 changed files with 3296935 additions and 282 deletions

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src_SSITH_P3/Verilog_RTL/mkDebug_Module.v Normal file

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