diff --git a/src_Core/CHERI/ScrFile.bsv b/src_Core/CHERI/ScrFile.bsv
index 85900d0..161d037 100644
--- a/src_Core/CHERI/ScrFile.bsv
+++ b/src_Core/CHERI/ScrFile.bsv
@@ -146,7 +146,7 @@ module mkScrFile (ScrFile);
     Reg#(CapReg) stcc_reg      <- mkCsrReg(defaultValue);
     Reg#(CapReg) stdc_reg      <- mkCsrReg(nullCap);
     Reg#(CapReg) sScratchC_reg <- mkCsrReg(nullCap);
-    Reg#(CapReg) sepcc_reg     <- mkCsrReg(defaultValue);
+    Ehr#(2, CapReg) sepcc_reg  <- mkConfigEhr(defaultValue);
 
     // Machine level SCRs with accessSysRegs
     Reg#(CapReg) mtcc_reg      <- mkCsrReg(defaultValue);
@@ -169,7 +169,7 @@ module mkScrFile (ScrFile);
             SCR_STCC:      stcc_reg;
             SCR_STDC:      stdc_reg;
             SCR_SScratchC: sScratchC_reg;
-            SCR_SEPCC:     sepcc_reg;
+            SCR_SEPCC:     sepcc_reg[1];
             // Machine CSRs with accessSysRegs
             SCR_MTCC:      mtcc_reg;
             SCR_MTDC:      mtdc_reg;
@@ -190,7 +190,11 @@ module mkScrFile (ScrFile);
     endmethod
 
     method ActionValue#(Scr_Trap_Updates) trap(CapPipe pc, Bit#(2) prv);
-        mepcc_reg[0] <= cast(pc);
+        case (prv)
+            prvM: mepcc_reg[0] <= cast(pc);
+            prvS: mepcc_reg[0] <= cast(pc);
+            prvU: mepcc_reg[0] <= cast(pc);
+        endcase
         return Scr_Trap_Updates{new_pcc: cast(mtcc_reg)};
     endmethod
 
@@ -199,7 +203,7 @@ module mkScrFile (ScrFile);
     endmethod
 
     method ActionValue#(Scr_RET_Updates) sret;
-        return Scr_RET_Updates{new_pcc: cast(mepcc_reg[0])};
+        return Scr_RET_Updates{new_pcc: cast(sepcc_reg[0])};
     endmethod
 
     method ScrVMInfo ddcCheck;
diff --git a/src_Core/RISCY_OOO/procs/lib/Decode.bsv b/src_Core/RISCY_OOO/procs/lib/Decode.bsv
index a534269..9b31c4e 100755
--- a/src_Core/RISCY_OOO/procs/lib/Decode.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Decode.bsv
@@ -375,7 +375,7 @@ function DecodeResult decode(Instruction inst);
             dInst.capChecks.check_authority_src = Src1;
             dInst.capChecks.check_low_src = Src1Addr;
             dInst.capChecks.check_high_src = Src1AddrPlus2;
-            dInst.capChecks.check_inclusive = False;
+            dInst.capChecks.check_inclusive = True;
         end
 
         Jalr: begin
@@ -390,7 +390,7 @@ function DecodeResult decode(Instruction inst);
             dInst.capChecks.check_authority_src = Src1;
             dInst.capChecks.check_low_src = Src1Addr;
             dInst.capChecks.check_high_src = Src1AddrPlus2;
-            dInst.capChecks.check_inclusive = False;
+            dInst.capChecks.check_inclusive = True;
         end
 
         Branch: begin
@@ -412,7 +412,7 @@ function DecodeResult decode(Instruction inst);
             dInst.capChecks.check_authority_src = Src1;
             dInst.capChecks.check_low_src = Src1Addr;
             dInst.capChecks.check_high_src = Src1AddrPlus2;
-            dInst.capChecks.check_inclusive = False;
+            dInst.capChecks.check_inclusive = True;
         end
 
         Load: begin
@@ -1143,7 +1143,7 @@ function DecodeResult decode(Instruction inst);
                                     dInst.capChecks.check_authority_src = Src1;
                                     dInst.capChecks.check_low_src = Src1Addr;
                                     dInst.capChecks.check_high_src = Src1AddrPlus2;
-                                    dInst.capChecks.check_inclusive = False;
+                                    dInst.capChecks.check_inclusive = True;
 
                                     dInst.iType = Jr;
                                     dInst.execFunc = tagged Br AT;