From 17a7a32092e241d14cdc6f1be8243b775e8aac81 Mon Sep 17 00:00:00 2001 From: jon Date: Tue, 15 Dec 2020 16:18:36 +0000 Subject: [PATCH] Use DRegOR instead of immitating latching behaviour. --- src_Core/CPU/Core.bsv | 10 +++------ src_Core/RISCY_OOO/coherence/src/IBank.bsv | 10 +++------ src_Core/RISCY_OOO/coherence/src/L1Bank.bsv | 10 +++------ .../procs/RV64G_OOO/MemExePipeline.bsv | 22 ++++++++----------- 4 files changed, 18 insertions(+), 34 deletions(-) diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv index 1066279..0085c35 100644 --- a/src_Core/CPU/Core.bsv +++ b/src_Core/CPU/Core.bsv @@ -61,7 +61,7 @@ import VerificationPacket::*; import Performance::*; `ifdef PERFORMANCE_MONITORING import PerformanceMonitor::*; -import SpecialWires::*; +import BlueUtils::*; `endif import HasSpecBits::*; import Exec::*; @@ -278,11 +278,7 @@ module mkCore#(CoreId coreId)(Core); `endif `ifdef PERFORMANCE_MONITORING - Array #(Wire #(EventsCore)) hpm_core_events <- mkDWireOR (5, unpack (0)); - Reg #(EventsCore) hpm_core_events_reg <- mkConfigReg(unpack(0)); - rule update_hpm_core_events_reg; - hpm_core_events_reg <= hpm_core_events[0]; - endrule + Array #(Reg #(EventsCore)) hpm_core_events <- mkDRegOR (5, unpack (0)); `endif // ================================================================ @@ -1117,7 +1113,7 @@ module mkCore#(CoreId coreId)(Core); Vector #(1, Bit #(Report_Width)) null_evt = replicate (0); Vector #(31, Bit #(Report_Width)) mem_core_evts_vec = to_large_vector (coreFix.memExeIfc.events); - Vector #(31, Bit #(Report_Width)) other_core_evts_vec = to_large_vector (hpm_core_events_reg); + Vector #(31, Bit #(Report_Width)) other_core_evts_vec = to_large_vector (hpm_core_events[0]); Vector #(31, Bit #(Report_Width)) core_evts_vec = unpack(pack(mem_core_evts_vec) | pack(other_core_evts_vec)); Vector #(16, Bit #(Report_Width)) imem_evts_vec = to_large_vector (iMem.events); Vector #(16, Bit #(Report_Width)) dmem_evts_vec = to_large_vector (dMem.events); diff --git a/src_Core/RISCY_OOO/coherence/src/IBank.bsv b/src_Core/RISCY_OOO/coherence/src/IBank.bsv index b65da88..ef1bf10 100644 --- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv @@ -59,7 +59,7 @@ import LatencyTimer::*; import RandomReplace::*; `ifdef PERFORMANCE_MONITORING import PerformanceMonitor::*; -import SpecialWires::*; +import BlueUtils::*; `endif export ICRqStuck(..); @@ -193,11 +193,7 @@ module mkIBank#( Count#(Data) ldMissLat <- mkCount(0); `endif `ifdef PERFORMANCE_MONITORING - Array #(Wire #(EventsCache)) perf_events <- mkDWireOR (2, unpack (0)); - Reg #(EventsCache) perf_events_reg <- mkConfigReg(unpack(0)); - rule update_events_reg; - perf_events_reg <= perf_events[0]; - endrule + Array #(Reg #(EventsCache)) perf_events <- mkDRegOR (2, unpack (0)); `endif function Action incrReqCnt; action @@ -846,7 +842,7 @@ module mkIBank#( endcase); endmethod `ifdef PERFORMANCE_MONITORING - method EventsCache events = perf_events_reg; + method EventsCache events = perf_events[0]; `endif endmodule diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv index 4dc503b..9e918f3 100644 --- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv @@ -62,7 +62,7 @@ import LatencyTimer::*; import RandomReplace::*; `ifdef PERFORMANCE_MONITORING import PerformanceMonitor::*; -import SpecialWires::*; +import BlueUtils::*; `endif export L1CRqStuck(..); @@ -212,11 +212,7 @@ module mkL1Bank#( Count#(Data) amoMissLat <- mkCount(0); `endif `ifdef PERFORMANCE_MONITORING - Array #(Wire #(EventsCache)) perf_events <- mkDWireOR (2, unpack (0)); - Reg #(EventsCache) perf_events_reg <- mkConfigReg(unpack(0)); - rule update_events_reg; - perf_events_reg <= perf_events[0]; - endrule + Array #(Reg #(EventsCache)) perf_events <- mkDRegOR (2, unpack (0)); `endif function Action incrReqCnt(MemOp op); action @@ -1130,7 +1126,7 @@ endfunction endcase); endmethod `ifdef PERFORMANCE_MONITORING - method EventsCache events = perf_events_reg; + method EventsCache events = perf_events[0]; `endif endmodule diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index 1f34878..39ceb05 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -71,7 +71,7 @@ import ISA_Decls_CHERI::*; import CacheUtils::*; `ifdef PERFORMANCE_MONITORING import PerformanceMonitor::*; -import SpecialWires::*; +import BlueUtils::*; `endif import Cur_Cycle :: *; @@ -276,11 +276,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); `endif `ifdef PERFORMANCE_MONITORING - Array #(Wire #(EventsCoreMem)) events_wire <- mkDWireOR (5, unpack (0)); - Reg #(EventsCoreMem) events_reg <- mkReg(unpack(0)); - rule update_events_reg; - events_reg <= events_wire[0]; - endrule + Array #(Reg #(EventsCoreMem)) events_reg <- mkDRegOR (5, unpack (0)); `endif // reservation station @@ -353,7 +349,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); EventsCoreMem events = unpack(0); events.evt_LOAD_WAIT = saturating_truncate(lat); events.evt_MEM_CAP_LOAD_TAG_SET = (d.tag) ? 1 : 0; - events_wire[1] <= events; + events_reg[1] <= events; `endif endmethod method Action respLrScAmo(DProcReqId id, MemTaggedData d); @@ -381,7 +377,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); EventsCoreMem events = unpack(0); if (waitSt.shiftedBE == -1) events.evt_MEM_CAP_STORE = 1; events.evt_STORE_WAIT = saturating_truncate(lat); - events_wire[2] <= events; + events_reg[2] <= events; `endif // now figure out the data to be written Vector#(LineSzData, ByteEn) be = replicate(replicate(False)); @@ -407,7 +403,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); EventsCoreMem events = unpack(0); if (pack(e.byteEn) == -1) events.evt_MEM_CAP_STORE = 1; events.evt_STORE_WAIT = saturating_truncate(lat); - events_wire[2] <= events; + events_reg[2] <= events; `endif return tuple2(unpack(pack(e.byteEn)), e.line); // return SB entry endmethod @@ -549,7 +545,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); `ifdef PERFORMANCE_MONITORING EventsCoreMem events = unpack(0); events.evt_MEM_CAP_STORE_TAG_SET = (d.tag) ? 1 : 0; - events_wire[4] <= events; + events_reg[4] <= events; `endif end @@ -760,7 +756,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); doAssert(False, "load is stalled"); end `ifdef PERFORMANCE_MONITORING - events_wire[0] <= events; + events_reg[0] <= events; `endif endaction endfunction @@ -1332,7 +1328,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); `ifdef PERFORMANCE_MONITORING EventsCoreMem events = unpack(0); events.evt_SC_SUCCESS = 1; - events_wire[3] <= events; + events_reg[3] <= events; `endif endrule @@ -1566,6 +1562,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); endcase); endmethod `ifdef PERFORMANCE_MONITORING - method events = events_reg; + method events = events_reg[0]; `endif endmodule