From d3e8ef8d900c5afcd7180c222d8231b6927e6302 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 25 Jul 2022 13:18:50 +0100 Subject: [PATCH] removed unnecessary declarations in RenameStage --- src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index b0b6c04..0102058 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -735,7 +735,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); doAssert(!isValid(dInst.csr), "Mem never explicitly read/write CSR"); doAssert((dInst.iType != Fence) == isValid(dInst.imm), "Mem (non-Fence) needs imm for virtual addr"); - Bit#(16) dum = hash(getAddr(pc)); // put in ldstq if(isLdQ) begin lsq.enqLd(inst_tag, mem_inst, allow_cap, phy_regs.dst, spec_bits, hash(getAddr(pc))); @@ -1071,7 +1070,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); "Mem (non-Fence) needs imm for virtual addr"); doAssert(!isValid(spec_tag), "should not have spec tag"); // put in ldstq - Bit#(16) dum = hash(getAddr(pc)); if(isLdQ) begin lsq.enqLd(inst_tag, mem_inst, phy_regs.dst, spec_bits, hash(getAddr(pc))); end