Add capability-aware compressed decoding

2021-04-14 14:56:19 +01:00
parent 88751cccba
commit 1b5f4ee9e0
3 changed files with 294 additions and 242 deletions
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -626,7 +626,7 @@ module mkFetchStage(FetchStage);
               end
            end else if (is_16b_inst(frag.inst_frag)) begin // 16-bit instruction
               new_pick = tagged Valid fetch3_2_instC(frag,
-                                                      fv_decode_C (misa, misa_mxl_64, frag.inst_frag),
+                                                      fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag),
                                                      zeroExtend(frag.inst_frag));
            end
         end