Fix debug module reset state machine

dmactive should only go low when the debug module has successfully reset. Approximate this by waiting for 1024 cycles, allowing any register access requests and system bus requests to come back.
2024-09-16 16:10:02 +01:00
parent 6fc7327b93
commit 1cfc58c2cc
3 changed files with 143 additions and 123 deletions
--- a/src_Core/Debug_Module/DM_Common.bsv
+++ b/src_Core/Debug_Module/DM_Common.bsv
@@ -26,6 +26,8 @@ DM_Addr max_DM_Addr = 'h5F;

 typedef Bit #(32) DM_Word;

+typedef Bit #(10) DM_Reset_Count;
+
 // ================================================================
 // Debug Module address map